Formal Verification of Circuits

1. Front Matter

   Pages i-x

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2. Introduction

   • Rolf Drechsler

   Pages 1-3

3. Notations and Definitions

   • Rolf Drechsler

   Pages 5-8

4. Decision Diagrams

   • Rolf Drechsler

   Pages 9-23

5. Theoretical Aspects of WLDDs

   • Rolf Drechsler

   Pages 25-40

6. Implementation of WLDDs

   • Rolf Drechsler

   Pages 41-56

7. Minimization of DDs

   • Rolf Drechsler

   Pages 57-129

8. Arithmetic Circuits

   • Rolf Drechsler

   Pages 131-156

9. Verification of HDLs

   • Rolf Drechsler

   Pages 157-164

10. Conclusions

    • Rolf Drechsler

    Pages 165-166

11. Back Matter

    Pages 167-179

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Formal verification has become one of the most important steps in circuit design. Since circuits can contain several million transistors, verification of such large designs becomes more and more difficult. Pure simulation cannot guarantee the correct behavior and exhaustive simulation is often impossible. However, many designs, like ALUs, have very regular structures that can be easily described at a higher level of abstraction. For example, describing (and verifying) an integer multiplier at the bit-level is very difficult, while the verification becomes easy when the outputs are grouped to build a bit-string. Recently, several approaches for formal circuit verification have been proposed that make use of these regularities. These approaches are based on Word-Level Decision Diagrams (WLDDs) which are graph-based representations of functions (similar to BDDs) that allow for the representation of functions with a Boolean range and an integer domain.
Formal Verification of Circuits is devoted to the discussion of recent developments in the field of decision diagram-based formal verification. Firstly, different types of decision diagrams (including WLDDs) are introduced and theoretical properties are discussed that give further insight into the data structure. Secondly, implementation and minimization concepts are presented. Applications to arithmetic circuit verification and verification of designs specified by hardware description languages are described to show how WLDDs work in practice.
Formal Verification of Circuits is intended for CAD developers and researchers as well as designers using modern verification tools. It will help people working with formal verification (in industry or academia) to keep informed about recent developments in this area.

• Hardware
• Hardwarebeschreibungssprache
• circuit design
• computer-aided design (CAD)
• formal verification
• simulation
• transistor
• verification

From the reviews:

"This monograph addresses the problem of formal verification for circuits using as a conceptual tool the Word-Level Decision Diagrams (WLDDs). … The book offers a concise discussion of the field of WLDD-based formal verification of circuits. … The book is written in a clear style and represents an easy-to-read introduction into the area of word-level decision diagrams." (Marius Zimand, Zentralblatt MATH, Vol. 1062 (13), 2005)

• Albert-Ludwigs-University, Freiburg, Germany

  Rolf Drechsler

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