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The Verilog® Hardware Description Language

  • Book
  • © 1998

Overview

Authors:
  1. Donald E. Thomas

    1. Carnegie Mellon University, USA

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    You can also search for this author in PubMed   Google Scholar

  2. Philip R. Moorby

    1. Synapix, Inc., USA

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    You can also search for this author in PubMed   Google Scholar

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Table of contents (10 chapters)

  1. Front Matter

    Pages i-xix
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  2. Verilog—A Tutorial Introduction

    • Donald E. Thomas, Philip R. Moorby
    Pages 1-45

  3. Behavioral Modeling

    • Donald E. Thomas, Philip R. Moorby
    Pages 47-79

  4. Concurrent Processes

    • Donald E. Thomas, Philip R. Moorby
    Pages 81-114

  5. Logic Level Modeling

    • Donald E. Thomas, Philip R. Moorby
    Pages 115-158

  6. Advanced Timing

    • Donald E. Thomas, Philip R. Moorby
    Pages 159-188

  7. Logic Synthesis

    • Donald E. Thomas, Philip R. Moorby
    Pages 189-212

  8. Behavioral Synthesis

    • Donald E. Thomas, Philip R. Moorby
    Pages 213-226

  9. User-Defined Primitives

    • Donald E. Thomas, Philip R. Moorby
    Pages 227-239

  10. Switch Level Modeling

    • Donald E. Thomas, Philip R. Moorby
    Pages 241-272

  11. Projects

    • Donald E. Thomas, Philip R. Moorby
    Pages 273-282

  12. Back Matter

    Pages 283-354
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Keywords

About this book

XV Acknowledgments xvii Chapter 1 Verilog - A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits II Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Behavioral Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines IS Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment("

Authors and Affiliations

  • Carnegie Mellon University, USA

    Donald E. Thomas

  • Synapix, Inc., USA

    Philip R. Moorby

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