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Table of contents (13 chapters)
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About this book
These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant while design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity.
Reuse Methodology Manual for System-On-A-Chip Designs outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process.
From the Foreword
`Synopsys and Mentor Graphics have joined forces to help make IP reuse a reality. One of the goals of our Design Reuse Partnership is to develop, demonstrate, and document a reuse-based design methodology that works. The Reuse Manual (RMM) is the result of this effort.'
Aart J. de Geus, Synopsys, Inc.
Walden C. Rhines, Mentor Graphics Corporation
Authors and Affiliations
Bibliographic Information
Book Title: Reuse Methodology Manual for System-On-A-Chip Designs
Authors: Michael Keating, Pierre Bricaud
DOI: https://doi.org/10.1007/978-1-4757-2887-3
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Springer-Verlag US 1998
eBook ISBN: 978-1-4757-2887-3Published: 09 March 2013
Edition Number: 1
Number of Pages: XVI, 224
Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design, Electrical Engineering, Computer Hardware