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Logic Synthesis Using Synopsys®

  • Book
  • © 1995

Overview

Authors:
  1. Pran Kurup

    1. Cirrus Logic, Inc., USA

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    You can also search for this author in PubMed   Google Scholar

  2. Taher Abbasi

    1. Synopsys, Inc., USA

    View author publications

    You can also search for this author in PubMed   Google Scholar

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Table of contents (8 chapters)

  1. Front Matter

    Pages i-xxi
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  2. High-Level Design Methodology Overview

    • Pran Kurup, Taher Abbasi
    Pages 1-35

  3. Coding in HDL for Synthesis

    • Pran Kurup, Taher Abbasi
    Pages 37-79

  4. Pre and Post-Synthesis Simulation

    • Pran Kurup, Taher Abbasi
    Pages 81-102

  5. Constraining and Optimizing Designs — I

    • Pran Kurup, Taher Abbasi
    Pages 103-161

  6. Constraining and Optimizing Designs — II

    • Pran Kurup, Taher Abbasi
    Pages 163-195

  7. Design for Testability

    • Pran Kurup, Taher Abbasi
    Pages 197-241

  8. Interfacing between CAD Tools

    • Pran Kurup, Taher Abbasi
    Pages 243-262

  9. Design Re-Use using DesignWare

    • Pran Kurup, Taher Abbasi
    Pages 263-278

  10. Back Matter

    Pages 279-304
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Keywords

About this book

Logic synthesis has become a fundamental component of the ASIC design flow, and Logic Synthesis Using Synopsys® has been written for all those who dislike reading manuals but who still like to learn logic synthesis as practised in the real world. The primary focus of the book is Synopsys Design Compiler®: the leading synthesis tool in the EDA marketplace. The book is specially organized to assist designers accustomed to schematic capture based design to develop the required expertise to effectively use the Compiler. Over 100 `classic scenarios' faced by designers using the Design Compiler have been captured and discussed, and solutions provided. The scenarios are based both on personal experiences and actual user queries. A general understanding of the problem-solving techniques provided will help the reader debug similar and more complicated problems. Furthermore, several examples and dc-shell scripts are provided.
Specifically, Logic Synthesis Using Synopsys® will help the reader develop a better understanding of the synthesis design flow, optimization strategies using the Design Compiler, test insertion using the Test Compiler®, commonly used interface formats such as EDIF and SDF, and design re-use in a synthesis-based design methodology. Examples have been provided in both VHDL and Verilog.
Audience: Written with CAD engineers in mind to enable them to formulate an effective synthesis-based ASIC design methodology. Will also assist design teams to better incorporate and effectively integrate synthesis with their existing in-house design methodology and CAD tools.

Authors and Affiliations

  • Cirrus Logic, Inc., USA

    Pran Kurup

  • Synopsys, Inc., USA

    Taher Abbasi

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