Overview
Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 177)
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Table of contents (12 chapters)
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Front Matter
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Back Matter
Keywords
About this book
High Level Synthesis of ASICs Under Timing and Synchronization Constraints addresses specific issues in applying high-level synthesis techniques to the design of ASICs. This complements previous results achieved in synthesis of general-purpose and signal processors, where data-path design is of utmost importance. In contrast, ASIC designs are often characterized by complex control schemes, to support communication and synchronization with the environment. The combined design of efficient data-path control-unit is the major contribution of this book.
Three requirements are important in modeling ASIC designs: concurrency, external synchronization, and detailed timing constraints. The objective of the research work presented here is to develop a hardware model incorporating these requirements as well as synthesis algorithms that operate on this hardware model.
The contributions of this book address both the theory and the implementation of algorithm for hardware synthesis.
Authors and Affiliations
Bibliographic Information
Book Title: High Level Synthesis of ASICs under Timing and Synchronization Constraints
Authors: David C. Ku, Giovanni Micheli
Series Title: The Springer International Series in Engineering and Computer Science
DOI: https://doi.org/10.1007/978-1-4757-2117-1
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Springer Science+Business Media New York 1992
Hardcover ISBN: 978-0-7923-9244-6Published: 31 May 1992
Softcover ISBN: 978-1-4419-5129-8Published: 19 November 2010
eBook ISBN: 978-1-4757-2117-1Published: 14 March 2013
Series ISSN: 0893-3405
Edition Number: 1
Number of Pages: XIV, 294
Topics: Circuits and Systems, Electrical Engineering, Computer-Aided Engineering (CAD, CAE) and Design