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Table of contents (11 chapters)
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Front Matter
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Introduction
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Back Matter
Keywords
About this book
The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors.
From the Foreword:
`With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits.'
Kurt Keutzer, University of California, Berkeley
Authors and Affiliations
Bibliographic Information
Book Title: Formal Equivalence Checking and Design Debugging
Authors: Shi-Yu Huang, Kwang-Ting (Tim) Cheng
Series Title: Frontiers in Electronic Testing
DOI: https://doi.org/10.1007/978-1-4615-5693-0
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Springer Science+Business Media New York 1998
Hardcover ISBN: 978-0-7923-8184-6Published: 30 June 1998
Softcover ISBN: 978-1-4613-7606-4Published: 30 September 2012
eBook ISBN: 978-1-4615-5693-0Published: 06 December 2012
Series ISSN: 0929-1296
Edition Number: 1
Number of Pages: XVIII, 229
Topics: Circuits and Systems, Artificial Intelligence, Electrical Engineering, Computer-Aided Engineering (CAD, CAE) and Design