Delay Fault Testing for VLSI Circuits

1. Front Matter

   Pages i-xii

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2. Introduction

   • Angela Krstić, Kwang-Ting Cheng

   Pages 1-5

3. Test Application Schemes for Testing Delay Defects

   • Angela Krstić, Kwang-Ting Cheng

   Pages 7-22

4. Delay Fault Models

   • Angela Krstić, Kwang-Ting Cheng

   Pages 23-31

5. Case Studies on Delay Testing

   • Angela Krstić, Kwang-Ting Cheng

   Pages 33-44

6. Path Delay Fault Classification

   • Angela Krstić, Kwang-Ting Cheng

   Pages 45-76

7. Delay Fault Simulation

   • Angela Krstić, Kwang-Ting Cheng

   Pages 77-100

8. Test Generation for Path Delay Faults

   • Angela Krstić, Kwang-Ting Cheng

   Pages 101-130

9. Design for Delay Fault Testability

   • Angela Krstić, Kwang-Ting Cheng

   Pages 131-155

10. Synthesis for Delay Fault Testability

    • Angela Krstić, Kwang-Ting Cheng

    Pages 157-168

11. Conclusions and Future Work

    • Angela Krstić, Kwang-Ting Cheng

    Pages 169-172

12. Back Matter

    Pages 173-191

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In the early days of digital design, we were concerned with the logical correctness of circuits. We knew that if we slowed down the clock signal sufficiently, the circuit would function correctly. With improvements in the semiconductor process technology, our expectations on speed have soared. A frequently asked question in the last decade has been how fast can the clock run. This puts significant demands on timing analysis and delay testing. Fueled by the above events, a tremendous growth has occurred in the research on delay testing. Recent work includes fault models, algorithms for test generation and fault simulation, and methods for design and synthesis for testability. The authors of this book, Angela Krstic and Tim Cheng, have personally contributed to this research. Now they do an even greater service to the profession by collecting the work of a large number of researchers. In addition to expounding such a great deal of information, they have delivered it with utmost clarity. To further the reader's understanding many key concepts are illustrated by simple examples. The basic ideas of delay testing have reached a level of maturity that makes them suitable for practice. In that sense, this book is the best x DELAY FAULT TESTING FOR VLSI CIRCUITS available guide for an engineer designing or testing VLSI systems. Tech­ niques for path delay testing and for use of slower test equipment to test high-speed circuits are of particular interest.

• VLSI
• computer-aided design (CAD)
• design
• integrated circuit
• modeling
• quality
• simulation
• stability

• University of California, Santa Barbara, USA

  Angela Krstić, Kwang-Ting Cheng

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