Skip to main content
SpringerLink
Log in

Formal Semantics and Proof Techniques for Optimizing VHDL Models

  • Book
  • © 1999

Overview

Authors:
  1. Kothanda Umamageswaran

    1. University of Cincinnati, USA

    View author publications

    You can also search for this author in PubMed   Google Scholar

  2. Sheetanshu L. Pandey

    1. University of Cincinnati, USA

    View author publications

    You can also search for this author in PubMed   Google Scholar

  3. Philip A. Wilsey

    1. University of Cincinnati, USA

    View author publications

    You can also search for this author in PubMed   Google Scholar

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 109.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (11 chapters)

  1. Front Matter

    Pages i-xxi
    Download chapter PDF

  2. Introduction

    • Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 1-5

  3. Related Work

    • Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 7-15

  4. The Static Model

    • Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 17-29

  5. A Well-Formed VHDL Model

    • Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 31-42

  6. The Reduction Algebra

    • Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 43-54

  7. Completeness of the Reduced Form

    • Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 55-64

  8. Interval Temporal Logic

    • Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 65-68

  9. The Dynamic Model

    • Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 69-88

  10. Applications of the Dynamic Model

    • Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 89-98

  11. A Framework for Proving Equivalences using PVS

    • Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 99-122

  12. Conclusions

    • Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey
    Pages 123-125

  13. Back Matter

    Pages 127-158
    Download chapter PDF
Back to top

Keywords

About this book

Formal Semantics and Proof Techniques for Optimizing VHDL Models presents a formal model of VHDL that clearly specifies both the static and dynamic semantics of VHDL. It provides a mathematical framework for representing VHDL constructs and shows how those constructs can be formally manipulated to reason about VHDL. The dynamic semantics is presented as a description of what the simulation of VHDL means. In particular it specifies what values the signals of a VHDL description will take if the description were to be executed. An advantage of the approach is that the semantic model can be used to validate different simulation algorithms. The book also presents an embedding of the dynamic semantics in a proof checker which is then used to prove equivalences of classes of VHDL descriptions.
Formal Semantics and Proof Techniques for Optimizing VHDL Models is written for hardware designers who are interested in the formal semantics of VHDL.

Authors and Affiliations

  • University of Cincinnati, USA

    Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey

Bibliographic Information

  • Book Title: Formal Semantics and Proof Techniques for Optimizing VHDL Models

  • Authors: Kothanda Umamageswaran, Sheetanshu L. Pandey, Philip A. Wilsey

  • DOI: https://doi.org/10.1007/978-1-4615-5123-2

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Springer Science+Business Media New York 1999

  • Hardcover ISBN: 978-0-7923-8375-8Published: 30 November 1998

  • Softcover ISBN: 978-1-4613-7331-5Published: 26 October 2012

  • eBook ISBN: 978-1-4615-5123-2Published: 06 December 2012

  • Edition Number: 1

  • Number of Pages: XXI, 158

  • Topics: Circuits and Systems, Computer Hardware, Computer-Aided Engineering (CAD, CAE) and Design, Electrical Engineering

Publish with us

Policies and ethics

Back to top

Search

Navigation