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Optimal VLSI Architectural Synthesis

Area, Performance and Testability

  • Book
  • © 1992

Overview

Authors:
  1. Catherine H. Gebotys

    1. University of Waterloo, Waterloo, Canada

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    You can also search for this author in PubMed   Google Scholar

  2. Mohamed I. Elmasry

    1. University of Waterloo, Waterloo, Canada

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    You can also search for this author in PubMed   Google Scholar

Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 158)

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Table of contents (13 chapters)

  1. Front Matter

    Pages i-xiv
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  2. Introduction

    1. Front Matter

      Pages 1-1
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    2. Global VLSI Design Cycle

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 3-20

    3. Behavioral and Structural Interfaces

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 21-36

  3. Review and Background

    1. Front Matter

      Pages 37-37
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    2. State of the Art Synthesis

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 39-61

    3. Introduction to Integer Programming

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 63-80

  4. Optimal Architectural Synthesis with Interfaces

    1. Front Matter

      Pages 81-81
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    2. A Methodology for Architectural Synthesis

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 83-95

    3. Simultaneous Scheduling, and Selection and Allocation of Functional Units

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 97-108

    4. Oasic: Area-Delay Constrained Architectural Synthesis

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 109-122

    5. Support for Algorithmic Constructs

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 123-128

    6. Interface Constraints

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 129-140

    7. Oasic Synthesis Results

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 141-175

  5. Testable Architectural Synthesis

    1. Front Matter

      Pages 177-177
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    2. Testability In Architectural Synthesis

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 179-205

    3. The Catree Architectural Synthesis with Testability

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 207-258

  6. Summary and Future Research

    1. Front Matter

      Pages 259-259
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    2. Summary and Future Research

      • Catherine H. Gebotys, Mohamed I. Elmasry
      Pages 261-270

  7. Back Matter

    Pages 271-289
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Keywords

About this book

Although research in architectural synthesis has been conducted for over ten years it has had very little impact on industry. This in our view is due to the inability of current architectural synthesizers to provide area-delay competitive (or "optimal") architectures, that will support interfaces to analog, asynchronous, and other complex processes. They also fail to incorporate testability. The OASIC (optimal architectural synthesis with interface constraints) architectural synthesizer and the CATREE (computer aided trees) synthesizer demonstrate how these problems can be solved. Traditionally architectural synthesis is viewed as NP hard and there­ fore most research has involved heuristics. OASIC demonstrates by using an IP approach (using polyhedral analysis), that most input algo­ rithms can be synthesized very fast into globally optimal architectures. Since a mathematical model is used, complex interface constraints can easily be incorporated and solved. Research in test incorporation has in general been separate from syn­ thesis research. This is due to the fact that traditional test research has been at the gate or lower level of design representation. Nevertheless as technologies scale down, and complexity of design scales up, the push for reducing testing times is increased. On way to deal with this is to incorporate test strategies early in the design process. The second half of this text examines an approach for integrating architectural synthesis with test incorporation. Research showed that test must be considered during synthesis to provide good architectural solutions which minimize Xlll area delay cost functions.

Authors and Affiliations

  • University of Waterloo, Waterloo, Canada

    Catherine H. Gebotys, Mohamed I. Elmasry

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