Sequential Logic Synthesis

1. Front Matter

   Pages i-1

   PDF

2. Introduction

   • Pranav Ashar, Srinivas Devadas, A. Richard Newton

   Pages 3-16

3. Basic Definitions and Concepts

   • Pranav Ashar, Srinivas Devadas, A. Richard Newton

   Pages 17-23

4. Encoding of Symbolic Inputs

   • Pranav Ashar, Srinivas Devadas, A. Richard Newton

   Pages 25-56

5. Encoding of Symbolic Outputs

   • Pranav Ashar, Srinivas Devadas, A. Richard Newton

   Pages 57-85

6. State Encoding

   • Pranav Ashar, Srinivas Devadas, A. Richard Newton

   Pages 87-116

7. Finite State Machine Decomposition

   • Pranav Ashar, Srinivas Devadas, A. Richard Newton

   Pages 117-168

8. Sequential Don’t Cares

   • Pranav Ashar, Srinivas Devadas, A. Richard Newton

   Pages 169-201

9. Conclusions and Directions for Future Work

   • Pranav Ashar, Srinivas Devadas, A. Richard Newton

   Pages 203-208

10. Back Matter

    Pages 209-225

    PDF

3. 2 Input Encoding Targeting Two-Level Logic . . . . . . . . 27 3. 2. 1 One-Hot Coding and Multiple-Valued Minimization 28 3. 2. 2 Input Constraints and Face Embedding 30 3. 3 Satisfying Encoding Constraints . . . . . . . 32 3. 3. 1 Definitions . . . . . . . . . . . . . . . 32 3. 3. 2 Column-Based Constraint Satisfaction 33 3. 3. 3 Row-Based Constraint Satisfaction . . 37 3. 3. 4 Constraint Satisfaction Using Dichotomies . 38 3. 3. 5 Simulated Annealing for Constraint Satisfaction 41 3. 4 Input Encoding Targeting Multilevel Logic. . 43 3. 4. 1 Kernels and Kernel Intersections . . . 44 3. 4. 2 Kernels and Multiple-Valued Variables 46 3. 4. 3 Multiple-Valued Factorization. . . . . 48 3. 4. 4 Size Estimation in Algebraic Decomposition . 53 3. 4. 5 The Encoding Step . 54 3. 5 Conclusion . . . . . . . . . 55 4 Encoding of Symbolic Outputs 57 4. 1 Heuristic Output Encoding Targeting Two-Level Logic. 59 4. 1. 1 Dominance Relations. . . . . . . . . . . . . . . . 59 4. 1. 2 Output Encoding bythe Derivation of Dominance Relations . . . . . . . . . . . . . . . . . . . . . 60 . . 4. 1. 3 Heuristics to Minimize the Number of Encoding Bits . . . . . . . . . . . . 64 4. 1. 4 Disjunctive Relationships . . . . . . . . . . . 65 4. 1. 5 Summary . . . . . . . . . . . . . . . . . . 66 . . 4. 2 Exact Output Encoding Targeting Two-Level Logic. 66 4. 2. 1 Generation of Generalized Prime Implicants . 68 4. 2. 2 Selecting a Minimum Encodeable Cover . . . 68 4. 2. 3 Dominance and Disjunctive Relationships to S- isfy Constraints . . . . . . . . . . . 70 4. 2. 4 Constructing the Optimized Cover 73 4. 2. 5 Correctness of the Procedure . . 73 4. 2. 6 Multiple Symbolic Outputs . . .

• VLSI
• algorithms
• automata
• complexity
• computer
• computer-aided design (CAD)
• interconnect
• logic
• modeling
• optimization
• stability

• University of California, Berkeley, USA

  Pranav Ashar, A. Richard Newton

• Massachusetts Institute of Technology, USA

  Srinivas Devadas

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