Overview
Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 174)
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Table of contents (9 chapters)
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Front Matter
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Back Matter
Keywords
About this book
Matrix Computations on Systolic-Type Arrays provides a much needed description of the area of processor arrays for matrix algorithms and of the methods used to derive those arrays. The ideas developed here reduce the space of solutions in the design/mapping process by establishing clear criteria to select among possible options as well as by a-priori rejection of alternatives which are not adequate (but which are considered in other approaches). The end result is a method which is more specific than other techniques previously available (suitable for a class of matrix algorithms) but which is more systematic, better defined and more effective in reaching the desired objectives.
Matrix Computations on Systolic-Type Arrays will interest researchers and professionals who are looking for systematic mechanisms to implement matrix algorithms either as algorithm-specific structures or using specialized architectures. It provides tools that simplify the design/mapping process without introducing degradation, and that permit tradeoffs between performance/cost measures selected by the designer.
Authors and Affiliations
Bibliographic Information
Book Title: Matrix Computations on Systolic-Type Arrays
Authors: Jaime H. Moreno, Tomás Lang
Series Title: The Springer International Series in Engineering and Computer Science
DOI: https://doi.org/10.1007/978-1-4615-3610-9
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Springer Science+Business Media New York 1992
Hardcover ISBN: 978-0-7923-9237-8Published: 31 October 1992
Softcover ISBN: 978-1-4613-6604-1Published: 30 September 2012
eBook ISBN: 978-1-4615-3610-9Published: 06 December 2012
Series ISSN: 0893-3405
Edition Number: 1
Number of Pages: XXVII, 280
Topics: Circuits and Systems, Signal, Image and Speech Processing, Electrical Engineering, Processor Architectures