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Table of contents (11 chapters)
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Front Matter
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Back Matter
About this book
Potentially one of the most important techniques involves combining architecture optimization with voltage scaling, allowing a trade-off between silicon area and low-power operation. Architectural optimization enables supply voltages of the order of 1 V using standard CMOS technology. Several techniques can also be used to minimize the switched capacitance, including representation, optimizing signal correlations, minimizing spurious transitions, optimizing sequencing of operations, activity-driven power down, etc. The high- efficiency of DC-DC converter circuitry required for efficient, low-voltage and low-current level operation is described by Stratakos, Sullivan and Sanders. The application of various low-power techniques to a chip set for multimedia applications shows that orders-of-magnitude reduction in power consumption is possible.
The book also features an analysis by Professor Meindl of the fundamental limits of power consumption achievable at all levels of the design hierarchy. Svensson, of ISI, describes emerging adiabatic switching techniques that can break the CV2f barrier and reduce the energy per computation at a fixed voltage. Srivastava, of AT&T, presents the application of aggressive shut-down techniques to microprocessor applications.
Authors and Affiliations
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Massachusetts Institute of Technology, USA
Anantha P. Chandrakasan
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University of California/Berkeley, USA
Robert W. Brodersen
Bibliographic Information
Book Title: Low Power Digital CMOS Design
Authors: Anantha P. Chandrakasan, Robert W. Brodersen
DOI: https://doi.org/10.1007/978-1-4615-2325-3
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Springer Science+Business Media New York 1995
Hardcover ISBN: 978-0-7923-9576-8Published: 30 June 1995
Softcover ISBN: 978-1-4613-5984-5Published: 04 October 2012
eBook ISBN: 978-1-4615-2325-3Published: 06 December 2012
Edition Number: 1
Number of Pages: XI, 409