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  • Book
  • © 2001

Area Array Interconnection Handbook

Editors:

  1. Karl J. Puttlitz
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    You can also search for this editor in PubMed   Google Scholar

  2. Paul A. Totta
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    You can also search for this editor in PubMed   Google Scholar

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Table of contents (28 chapters)

  1. Front Matter

    Pages i-lxviii
    PDF

  2. History of Flip Chip and Area Array Technology

  3. Chip-Level Technology

    1. Front Matter

      Pages 37-37
      PDF

    2. Wafer Bumping

      • Paul Totta, Glenn Rinne, Peter Elenius, Michael Varnau, Thomas Oppert, Elke Zakel et al.
      Pages 39-116

    3. Wafer-Level Test

      • Gobinda Das, Franco Motika, Eugene Atwood
      Pages 117-148

    4. Known Good Die (KGD)

      • Claude L. Bertin, Lo-Soun Su, Jody Van Horn
      Pages 149-200

    5. Wafer Finishing—Dicing,Picking,Shipping

      • Lyman R. Clark, Mark Brown, Scott Evans, Steve Bedore, Charles E. Gutentag, Robert A. Sierra
      Pages 201-227

    6. Ceramic Chip Carriers

      • John U. Knickerbocker, Thomas F. Redmond
      Pages 228-267

    7. Laminate/HDI Die Carriers

      • Happy T. Holden, Donald Barr, Douglas Powell
      Pages 268-314

    8. Flip-Chip Die Attach Technology

      • Peter J. Brofman, Karl J. Puttlitz, Kathleen A. Stalter, Charles Woychik
      Pages 315-349

    9. Solder Bump Flip-Chip Replacement Technology on Ceramic Carriers

      • Karl J. Puttlitz, Kathleen A. Stalter
      Pages 350-370

    10. Manufacturing Considerations and Tools for Flip Chip Assembly

      • David L. Edwards, Barrie C. Campbell, James H. Covell II, Kenneth C. Marston, Camille Proietti-Bowne
      Pages 371-420

    11. Test and Burn-in Sockets

      • Eugene Atwood, Glenn Daves
      Pages 421-451

    12. Underfill: The Enabling Technology for Flip-Chip Packaging

      • Stephen L. Buchwalter, Maurice E. Edwards, Daniel Gamota, Michael A. Gaynes, Son K. Tran
      Pages 452-499

    13. Reliability of Die-Level Interconnections

      • Giulio DiGiacomo, Jasvir S. Jaspal
      Pages 500-548

  4. Package-Level Technology

    1. Front Matter

      Pages 549-549
      PDF

    2. Ceramic and Plastic Pin Grid Array Technology

      • Balaram Ghosal, Richard Sigliano, Y. Kunimatsu
      Pages 551-576

    3. Plastic Ball Grid Array

      • Mark J. Kuzawinski, Thomas R. Homa
      Pages 577-613

    4. Tape Ball Grid Array

      • Frank Andros
      Pages 614-655

    5. Ceramic Ball and Column Grid Arrays

      • Marie S. Cole, Karl J. Puttlitz, Robert Lanzone
      Pages 656-701
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About this book

Microelectronic packaging has been recognized as an important "enabler" for the solid­ state revolution in electronics which we have witnessed in the last third of the twentieth century. Packaging has provided the necessary external wiring and interconnection capability for transistors and integrated circuits while they have gone through their own spectacular revolution from discrete device to gigascale integration. At IBM we are proud to have created the initial, simple concept of flip chip with solder bump connections at a time when a better way was needed to boost the reliability and improve the manufacturability of semiconductors. The basic design which was chosen for SLT (Solid Logic Technology) in the 1960s was easily extended to integrated circuits in the '70s and VLSI in the '80s and '90s. Three I/O bumps have grown to 3000 with even more anticipated for the future. The package families have evolved from thick-film (SLT) to thin-film (metallized ceramic) to co-fired multi-layer ceramic. A later family or ceramics with matching expansivity to sili­ con and copper internal wiring was developed as a predecessor of the chip interconnection revolution in copper, multilevel, submicron wiring. Powerful server packages have been de­ veloped in which the combined chip and package copper wiring exceeds a kilometer. All of this was achieved with the constant objective of minimizing circuit delays through short, efficient interconnects.
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Keywords

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Bibliographic Information

  • Book Title: Area Array Interconnection Handbook

  • Editors: Karl J. Puttlitz, Paul A. Totta

  • DOI: https://doi.org/10.1007/978-1-4615-1389-6

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Kluwer Academic Publishers 2001

  • Hardcover ISBN: 978-0-7923-7919-5Due: 31 October 2001

  • Softcover ISBN: 978-1-4613-5529-8Published: 12 November 2012

  • eBook ISBN: 978-1-4615-1389-6Published: 06 December 2012

  • Edition Number: 1

  • Number of Pages: CXXXVI, 1188

  • Topics: Circuits and Systems, Manufacturing, Machines, Tools, Processes, Climate Change, Electrical Engineering

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Buy it now

eBook USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

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