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Residue Number Systems

Algorithms and Architectures

  • Book
  • © 2002

Overview

Authors:
  1. P. V. Ananda Mohan

    1. I.T.I. Limited, Bangalore, India

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Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 677)

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Table of contents (9 chapters)

  1. Front Matter

    Pages i-xiii
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  2. Introduction

    • P. V. Ananda Mohan
    Pages 2-10

  3. Forward and Reverse Converters for General Moduli Sets

    • P. V. Ananda Mohan
    Pages 11-57

  4. Forward and Reverse Converters for The Moduli Set {2k-1, 2k, 2k+1}

    • P. V. Ananda Mohan
    Pages 59-96

  5. Multipliers For RNS

    • P. V. Ananda Mohan
    Pages 97-144

  6. Base Extension, Scaling and Division Techniques

    • P. V. Ananda Mohan
    Pages 145-169

  7. Error Detection and Correction in RNS

    • P. V. Ananda Mohan
    Pages 171-186

  8. Quadratic Residue Number Systems

    • P. V. Ananda Mohan
    Pages 187-198

  9. Applications of Residue Number Systems

    • P. V. Ananda Mohan
    Pages 199-234

  10. References

    • P. V. Ananda Mohan
    Pages 235-251

  11. Back Matter

    Pages 253-254
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Keywords

About this book

There has been continuing interest in the improvement of the speed of Digital Signal processing. The use of Residue Number Systems for the design of DSP systems has been extensively researched in literature. Szabo and Tanaka have popularized this approach through their book published in 1967. Subsequently, Jenkins and Leon have rekindled the interest of researchers in this area in 1978, from which time there have been several efforts to use RNS in practical system implementation. An IEEE Press book has been published in 1986 which was a collection of Papers. It is very interesting to note that in the recent past since 1988, the research activity has received a new thrust with emphasis on VLSI design using non­ ROM based designs as well as ROM based designs as evidenced by the increased publications in this area. The main advantage in using RNS is that several small word-length Processors are used to perform operations such as addition, multiplication and accumulation, subtraction, thus needing less instruction execution time than that needed in conventional 16 bitl32 bit DSPs. However, the disadvantages of RNS have b. een the difficulty of detection of overflow, sign detection, comparison of two numbers, scaling, and division by arbitrary number, RNS to Binary conversion and Binary to RNS conversion. These operations, unfortunately, are computationally intensive and are time consuming.

Authors and Affiliations

  • I.T.I. Limited, Bangalore, India

    P. V. Ananda Mohan

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