Authors:
- Covers both SystemVerilog Assertions and Sytem Verilog Functional Coverage language and methodologies
- Provides practical examples of the what, how and why of Assertion Based Verification and Functional Coverage methodologies
- Explains each concept in an easy to understand, step-by-step fashion and applies it to a real example
- Includes 6 practical LABs that enable readers to put in practice the concepts explained in the book
- Includes supplementary material: sn.pub/extras
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Table of contents (22 chapters)
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Front Matter
About this book
Authors and Affiliations
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Los Gatos, USA
Ashok B. Mehta
About the author
Ashok Mehta is a senior manager in TSMC's CPU/SoC Architecture and Methodology group working on System and 3DIC design projects. In the past, Ashok worked in engineering and management positions at DEC, Data General, Intel and AMCC. He has extensive experience in Design/Verification of complex SoC and Processor devices. He holds nine US patents on ESL and 3DIC designs. Ashok holds a MSEE from University of Missouri.
Bibliographic Information
Book Title: SystemVerilog Assertions and Functional Coverage
Book Subtitle: Guide to Language, Methodology and Applications
Authors: Ashok B. Mehta
DOI: https://doi.org/10.1007/978-1-4614-7324-4
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media New York 2014
Hardcover ISBN: 978-1-4614-7323-7
eBook ISBN: 978-1-4614-7324-4
Edition Number: 1
Number of Pages: XXXIII, 356
Topics: Circuits and Systems, Electronics and Microelectronics, Instrumentation, Processor Architectures