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Designing TSVs for 3D Integrated Circuits

  • Book
  • © 2013

Overview

Authors:
  1. Nauman Khan

    1. Tufts University, Medford, USA

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  2. Soha Hassoun

    1. , Department of Computer Science, Tufts University, Medford, USA

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    You can also search for this author in PubMed   Google Scholar

  • Introduces readers to challenges and best practices in designing TSVs for 3D integrated circuits
  • Discusses how TSVs induce noise affecting neighboring devices, provides a methodology to evaluate noise and evaluates several techniques to eliminate and reduce TSV noise
  • Investigates the impact of TSV size and granularity on power delivery for 3D ICs within a novel framework that considers architectural setups and benchmarks
  • Explores the use of Carbon Nanotubes for power grid design

Part of the book series: SpringerBriefs in Electrical and Computer Engineering (BRIEFSELECTRIC)

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Table of contents (7 chapters)

  1. Front Matter

    Pages i-x
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  2. Introduction

    • Nauman Khan, Soha Hassoun
    Pages 1-5

  3. Background

    • Nauman Khan, Soha Hassoun
    Pages 7-14

  4. Analysis and Mitigation of TSV-Induced Substrate Noise

    • Nauman Khan, Soha Hassoun
    Pages 15-26

  5. TSVs for Power Delivery

    • Nauman Khan, Soha Hassoun
    Pages 27-41

  6. Early Estimation of TSV Area for Power Delivery in 3-D ICs

    • Nauman Khan, Soha Hassoun
    Pages 43-51

  7. Carbon Nanotubes for Advancing TSV Technology

    • Nauman Khan, Soha Hassoun
    Pages 53-62

  8. Conclusions and Future Directions

    • Nauman Khan, Soha Hassoun
    Pages 63-65

  9. Back Matter

    Pages 67-76
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Keywords

About this book

This book explores the challenges and presents best strategies for designing Through-Silicon Vias (TSVs) for 3D integrated circuits.  It describes a novel technique to mitigate TSV-induced noise, the GND Plug, which is superior to others adapted from 2-D planar technologies, such as a backside ground plane and traditional substrate contacts. The book also investigates, in the form of a comparative study, the impact of TSV size and granularity, spacing of C4 connectors, off-chip power delivery network, shared and dedicated TSVs, and coaxial TSVs on the quality of power delivery in 3-D ICs. The authors provide detailed best design practices for designing 3-D power delivery networks.  Since TSVs occupy silicon real-estate and impact device density, this book provides four iterative algorithms to minimize the number of TSVs in a power delivery network. Unlike other existing methods, these algorithms can be applied in early design stages when only functional block- level behaviors and a floorplan are available. Finally, the authors explore the use of Carbon Nanotubes for power grid design as a futuristic alternative to Copper.

Authors and Affiliations

  • Tufts University, Medford, USA

    Nauman Khan

  • , Department of Computer Science, Tufts University, Medford, USA

    Soha Hassoun

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