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High Performance Multi-Channel High-Speed I/O Circuits

  • Book
  • © 2014

Overview

Authors:
  1. Taehyoun Oh

    1. Department of ECE, University of Minnesota, Minneapolis, USA

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  2. Ramesh Harjani

    1. Department of ECE, University of Minnesota, Minneapolis, USA

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    You can also search for this author in PubMed   Google Scholar

  • Describes technology and design ideas for power-efficient crosstalk cancellation in multi-channel high-speed I/O circuits
  • Includes critical background knowledge related to channel ISI equalization circuits
  • Provides crosstalk cancellation circuit methods that can be adapted efficiently to currently used equalization circuits in high-speed I/O receivers; key crosstalk cancellation blocks can be merged easily with automatic gain control (AGC) circuits in current I/O systems

Part of the book series: Analog Circuits and Signal Processing (ACSP)

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Table of contents (5 chapters)

  1. Front Matter

    Pages i-x
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  2. Introduction

    • Taehyoun Oh, Ramesh Harjani
    Pages 1-9

  3. \(2\times 6\) Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process

    • Taehyoun Oh, Ramesh Harjani
    Pages 11-25

  4. \(4 \times 12\) Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process

    • Taehyoun Oh, Ramesh Harjani
    Pages 27-46

  5. Adaptive XTCR, AGC, and Adaptive DFE Loop

    • Taehyoun Oh, Ramesh Harjani
    Pages 47-67

  6. Research Summary and Contributions

    • Taehyoun Oh, Ramesh Harjani
    Pages 69-71

  7. Back Matter

    Pages 73-89
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Keywords

About this book

This book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures.

Authors and Affiliations

  • Department of ECE, University of Minnesota, Minneapolis, USA

    Taehyoun Oh, Ramesh Harjani

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