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Microarchitecture of Network-on-Chip Routers

A Designer's Perspective

  • Book
  • © 2015

Overview

Authors:
  1. Giorgos Dimitrakopoulos

    1. Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, Greece

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  2. Anastasios Psarras

    1. Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, Greece

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    You can also search for this author in PubMed   Google Scholar

  3. Ioannis Seitanidis

    1. Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, Greece

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  • Designed pedagogically, explaining basic functionality of each NoC router and design block, relating it to the role it plays in the system
  • Performance-enhancing features are added in a step-by-step manner
  • Justifies and explains every design choice, including the less attractive options
  • Includes detailed examples presenting the flow of information inside the router on a cycle-by-cycle basis, highlighting the operation of each part under regular or worst-case traffic scenarios
  • Includes supplementary material: sn.pub/extras

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Table of contents (9 chapters)

  1. Front Matter

    Pages i-xiv
    Download chapter PDF

  2. Introduction to Network-on-Chip Design

    • Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis
    Pages 1-10

  3. Link-Level Flow Control and Buffering

    • Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis
    Pages 11-35

  4. Baseline Switching Modules and Routers

    • Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis
    Pages 37-59

  5. Arbitration Logic

    • Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis
    Pages 61-71

  6. Pipelined Wormhole Routers

    • Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis
    Pages 73-91

  7. Virtual-Channel Flow Control and Buffering

    • Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis
    Pages 93-109

  8. Baseline Virtual-Channel Based Switching Modules and Routers

    • Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis
    Pages 111-134

  9. High-Speed Allocators for VC-Based Routers

    • Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis
    Pages 135-147

  10. Pipelined Virtual-Channel-Based Routers

    • Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis
    Pages 149-169

  11. Back Matter

    Pages 171-175
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Keywords

About this book

This book provides a unified overview of network-on-chip router micro-architecture, the corresponding design opportunities and challenges, and existing solutions to overcome these challenges. The discussion focuses on the heart of a NoC, the NoC router, and how it interacts with the rest of the system. Coverage includes both basic and advanced design techniques that cover the entire router design space including router organization, flow control, pipelined operation, buffering architectures, as well as allocators’ structure and algorithms. Router micro-architectural options are presented in a step-by-step manner beginning from the basic design principles. Even highly sophisticated design alternatives are categorized and broken down to simpler pieces that can be understood easily and analyzed. This book is an invaluable reference for system, architecture, circuit, and EDA researchers and developers, who are interested in understanding the overall picture of NoC routers' architecture, the associated design challenges, and the available solutions.

Authors and Affiliations

  • Electrical and Computer Engineering, Democritus University of Thrace, Xanthi, Greece

    Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis

Bibliographic Information

  • Book Title: Microarchitecture of Network-on-Chip Routers

  • Book Subtitle: A Designer's Perspective

  • Authors: Giorgos Dimitrakopoulos, Anastasios Psarras, Ioannis Seitanidis

  • DOI: https://doi.org/10.1007/978-1-4614-4301-8

  • Publisher: Springer New York, NY

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer Science+Business Media New York 2015

  • Hardcover ISBN: 978-1-4614-4300-1

  • Softcover ISBN: 978-1-4939-4558-0

  • eBook ISBN: 978-1-4614-4301-8

  • Edition Number: 1

  • Number of Pages: XIV, 175

  • Number of Illustrations: 57 b/w illustrations, 77 illustrations in colour

  • Topics: Circuits and Systems, Electronics and Microelectronics, Instrumentation, Processor Architectures

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