Overview
- Provides practical solutions for delay and power reduction for on-chip interconnects and buses
- Focuses on Deep Sub micron technology devices and interconnects
- Offers in depth analysis of delay, including details regarding crosstalk and parasitics
- Describes use of the Schmitt Trigger as a versatile alternative approach to buffer insertion for delay and power reduction in VLSI interconnects
- Provides detailed simulation results to support the theoretical discussions
- Provides details of delay and power efficient bus coding techniques
Access this book
Tax calculation will be finalised at checkout
Other ways to access
Table of contents (5 chapters)
-
Front Matter
-
Basics of Interconnect Design
-
Front Matter
-
-
Buffer and Schmidt Trigger Insertion Techniques for Low Power Interconnect Design
-
Front Matter
-
-
Bus Coding Techniques for Low Power Interconnect Design
-
Front Matter
-
Keywords
About this book
Authors and Affiliations
Bibliographic Information
Book Title: Low Power Interconnect Design
Authors: Sandeep Saini
DOI: https://doi.org/10.1007/978-1-4614-1323-3
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media New York 2015
Hardcover ISBN: 978-1-4614-1322-6
Softcover ISBN: 978-1-4939-4294-7
eBook ISBN: 978-1-4614-1323-3
Edition Number: 1
Number of Pages: XVII, 152
Number of Illustrations: 99 b/w illustrations, 12 illustrations in colour
Topics: Circuits and Systems, Electronics and Microelectronics, Instrumentation, Processor Architectures