Overview
- Integrates power estimation and reduction for high level synthesis, with low-power, high-level design
- Shows specific techniques for ASICs as well as FPGA based SoC designs, allowing readers to evaluate and explore various possible alternatives
- Covers techniques from RTL/gate-level to hardware software co-design
Access this book
Tax calculation will be finalised at checkout
Other ways to access
Table of contents (13 chapters)
Keywords
About this book
Authors and Affiliations
Bibliographic Information
Book Title: Low Power Design with High-Level Power Estimation and Power-Aware Synthesis
Authors: Sumit Ahuja, Avinash Lakshminarayana, Sandeep Kumar Shukla
DOI: https://doi.org/10.1007/978-1-4614-0872-7
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media, LLC 2012
Hardcover ISBN: 978-1-4614-0871-0
Softcover ISBN: 978-1-4899-8780-8
eBook ISBN: 978-1-4614-0872-7
Edition Number: 1
Number of Pages: XXII, 170
Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design