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  • © 1999

Reuse Methodology Manual

For System-on-a-Chip Designs

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Table of contents (13 chapters)

  1. Front Matter

    Pages i-xxiii
  2. Introduction

    • Michael Keating, Pierre Bricaud
    Pages 1-10
  3. The System-on-a-Chip Design Process

    • Michael Keating, Pierre Bricaud
    Pages 11-24
  4. System-Level Design Issues: Rules and Tools

    • Michael Keating, Pierre Bricaud
    Pages 25-52
  5. The Macro Design Process

    • Michael Keating, Pierre Bricaud
    Pages 53-72
  6. RTL Coding Guidelines

    • Michael Keating, Pierre Bricaud
    Pages 73-125
  7. Macro Synthesis Guidelines

    • Michael Keating, Pierre Bricaud
    Pages 127-143
  8. Macro Verification Guidelines

    • Michael Keating, Pierre Bricaud
    Pages 145-170
  9. Developing Hard Macros

    • Michael Keating, Pierre Bricaud
    Pages 171-197
  10. Macro Deployment: Packaging for Reuse

    • Michael Keating, Pierre Bricaud
    Pages 199-206
  11. System Integration with Reusable Macros

    • Michael Keating, Pierre Bricaud
    Pages 207-228
  12. System-Level Verification Issues

    • Michael Keating, Pierre Bricaud
    Pages 229-251
  13. Data and Project Management

    • Michael Keating, Pierre Bricaud
    Pages 253-259
  14. Implementing a Reuse Process

    • Michael Keating, Pierre Bricaud
    Pages 261-276
  15. Back Matter

    Pages 277-286

About this book

Silicon technology now allows us to build chips consisting of tens of millions of transistors. This technology not only promises new levels of system integration onto a single chip, but also presents significant challenges to the chip designer. As a result, many ASIC developers and silicon vendors are re-examining their design methodologies, searching for ways to make effective use of the huge numbers of gates now available.
These designers see current design tools and methodologies as inadequate for developing million-gate ASICs from scratch. There is considerable pressure to keep design team size and design schedules constant even as design complexities grow. Tools are not providing the productivity gains required to keep pace with the increasing gate counts available from deep submicron technology. Design reuse - the use of pre-designed and pre-verified cores - is the most promising opportunity to bridge the gap between available gate-count and designer productivity.
Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition outlines an effective methodology for creating reusable designs for use in a System-on-a-Chip (SoC) design methodology. Silicon and tool technologies move so quickly that no single methodology can provide a permanent solution to this highly dynamic problem. Instead, this manual is an attempt to capture and incrementally improve on current best practices in the industry, and to give a coherent, integrated view of the design process. Reuse Methodology Manual for System-On-A-Chip Designs, Second Edition will be updated on a regular basis as a result of changing technology and improved insight into the problems of design reuse and its role in producing high-quality SoC designs.

Authors and Affiliations

  • Synopsys, Inc., USA

    Michael Keating

  • Mentor Graphics Corporation, USA

    Pierre Bricaud

Bibliographic Information

Buy it now

Buying options

eBook USD 39.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 54.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access