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Layout Minimization of CMOS Cells

  • Book
  • © 1992

Overview

Authors:
  1. Robert L. Maziasz

    1. The University of Michigan, USA

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    You can also search for this author in PubMed   Google Scholar

  2. John P. Hayes

    1. The University of Michigan, USA

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    You can also search for this author in PubMed   Google Scholar

Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 160)

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Table of contents (7 chapters)

  1. Front Matter

    Pages i-xiii
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  2. Introduction

    • Robert L. Maziasz, John P. Hayes
    Pages 1-25

  3. Functional Cell Layout Methods

    • Robert L. Maziasz, John P. Hayes
    Pages 27-48

  4. Series-Parallel Cell Width Minimization

    • Robert L. Maziasz, John P. Hayes
    Pages 49-75

  5. Planar Cell Width Minimization

    • Robert L. Maziasz, John P. Hayes
    Pages 77-103

  6. Single Cell Width and Height Minimization

    • Robert L. Maziasz, John P. Hayes
    Pages 105-132

  7. Cell Array Width and Height Minimization

    • Robert L. Maziasz, John P. Hayes
    Pages 133-152

  8. Conclusions

    • Robert L. Maziasz, John P. Hayes
    Pages 153-155

  9. Back Matter

    Pages 157-169
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Keywords

About this book

The layout of an integrated circuit (lC) is the process of assigning geometric shape, size and position to the components (transistors and connections) used in its fabrication. Since the number of components in modem ICs is enormous, computer­ aided-design (CAD) programs are required to automate the difficult layout process. Prior CAD methods are inexact or limited in scope, and produce layouts whose area, and consequently manufacturing costs, are larger than necessary. This book addresses the problem of minimizing exactly the layout area of an important class of basic IC structures called CMOS cells. First, we precisely define the possible goals in area minimization for such cells, namely width and height minimization, with allowance for area-reducing reordering of transistors. We reformulate the layout problem in terms of a graph model and develop new graph-theoretic concepts that completely characterize the fundamental area minimization problems for series-parallel and nonseries-parallel circuits. These concepts lead to practical algorithms that solve all the basic layout minimization problems exactly, both for a single cell and for a one-dimensional array of such cells. Although a few of these layout problems have been solved or partially solved previously, we present here the first complete solutions to all the problems of interest.

Authors and Affiliations

  • The University of Michigan, USA

    Robert L. Maziasz, John P. Hayes

Bibliographic Information

  • Book Title: Layout Minimization of CMOS Cells

  • Authors: Robert L. Maziasz, John P. Hayes

  • Series Title: The Springer International Series in Engineering and Computer Science

  • DOI: https://doi.org/10.1007/978-1-4615-3624-6

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Springer Science+Business Media New York 1992

  • Hardcover ISBN: 978-0-7923-9182-1Published: 31 October 1991

  • Softcover ISBN: 978-1-4613-6611-9Published: 28 September 2012

  • eBook ISBN: 978-1-4615-3624-6Published: 06 December 2012

  • Series ISSN: 0893-3405

  • Edition Number: 1

  • Number of Pages: XIII, 169

  • Topics: Electrical Engineering

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