Fast Simulation of Computer Architectures

1. Front Matter

   Pages i-ix

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2. Introduction

   • Thomas M. Conte, Charles E. Gimarc

   Pages 1-4

3. Shade: A Fast Instruction-Set Simulator for Execution Profiling

   • Bob Cmelik, David Keppel

   Pages 5-46

4. Instrumentation Tools

   • Jim Pierce, Michael D. Smith, Trevor Mudge

   Pages 47-86

5. Stack-Based Single-Pass Cache Simulation

   • Thomas M. Conte

   Pages 87-107

6. Non-Stack Single-Pass Simulation

   • Rabin A. Sugumar, Santosh G. Abraham

   Pages 109-144

7. Execution Driven Simulation of Shared Memory Multiprocessors

   • Bob Boothe

   Pages 145-170

8. Sampling for Cache and Processor Simulation

   • Kishore N. Menezes

   Pages 171-203

9. Performance Bounds for Rapid Computer System Evaluation

   • Bill Mangione-Smith

   Pages 205-237

10. Back Matter

    Pages 239-244

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Chapters in Fast Simulation of Computer Architectures cover topics such as how to collect traces, emulate instruction sets, simulate microprocessors using execution-driven techniques, evaluate memory hierarchies, apply statistical sampling to simulation, and how to augment simulation with performance bound models. The chapters have been written by many of the leading researchers in the area, in a collaboration that ensures that the material is both coherent and cohesive.
Audience: Of tremendous interest to practising computer architect designers seeking timely solutions to tough evaluation problems, and to advanced upper division undergraduate and graduate students of the field. Useful study aids are provided by the problems at the end of Chapters 2 through 8.

• architecture
• computer
• computer architecture
• processor

• University of South Carolina, Columbia, USA

  Thomas M. Conte

• AT & T Global Information Solutions, West Columbia, USA

  Charles E. Gimarc

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