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Design of High-Performance CMOS Voltage-Controlled Oscillators

  • Book
  • © 2003

Overview

Authors:
  1. Liang Dai

    1. Prominent Communications, Inc., San Diego, USA

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    You can also search for this author in PubMed   Google Scholar

  2. Ramesh Harjani

    1. Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, USA

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    You can also search for this author in PubMed   Google Scholar

Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 708)

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Table of contents (8 chapters)

  1. Front Matter

    Pages i-xix
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  2. Introduction

    • Liang Dai, Ramesh Harjani
    Pages 1-7

  3. Introduction to PLLs

    • Liang Dai, Ramesh Harjani
    Pages 9-26

  4. Phase Noise and Timing Jitter

    • Liang Dai, Ramesh Harjani
    Pages 27-37

  5. Review of Existing VCO Phase Noise Models

    • Liang Dai, Ramesh Harjani
    Pages 39-53

  6. Universal Model for Ring Oscillator Phase Noise

    • Liang Dai, Ramesh Harjani
    Pages 55-86

  7. New Ring VCO Design

    • Liang Dai, Ramesh Harjani
    Pages 87-106

  8. PLL Design Examples

    • Liang Dai, Ramesh Harjani
    Pages 107-148

  9. Conclusions

    • Liang Dai, Ramesh Harjani
    Pages 149-151

  10. Back Matter

    Pages 153-158
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Keywords

About this book

Design of High-Performance CMOS Voltage-Controlled Oscillators presents a phase noise modeling framework for CMOS ring oscillators. The analysis considers both linear and nonlinear operation. It indicates that fast rail-to-rail switching has to be achieved to minimize phase noise. Additionally, in conventional design the flicker noise in the bias circuit can potentially dominate the phase noise at low offset frequencies. Therefore, for narrow bandwidth PLLs, noise up conversion for the bias circuits should be minimized. We define the effective Q factor (Qeff) for ring oscillators and predict its increase for CMOS processes with smaller feature sizes. Our phase noise analysis is validated via simulation and measurement results.
The digital switching noise coupled through the power supply and substrate is usually the dominant source of clock jitter. Improving the supply and substrate noise immunity of a PLL is a challenging job in hostile environments such as a microprocessor chip where millions of digital gates are present.

Authors and Affiliations

  • Prominent Communications, Inc., San Diego, USA

    Liang Dai

  • Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, USA

    Ramesh Harjani

Bibliographic Information

  • Book Title: Design of High-Performance CMOS Voltage-Controlled Oscillators

  • Authors: Liang Dai, Ramesh Harjani

  • Series Title: The Springer International Series in Engineering and Computer Science

  • DOI: https://doi.org/10.1007/978-1-4615-1145-8

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Springer Science+Business Media New York 2003

  • Hardcover ISBN: 978-1-4020-7238-3Published: 31 October 2002

  • Softcover ISBN: 978-1-4613-5414-7Published: 31 October 2012

  • eBook ISBN: 978-1-4615-1145-8Published: 06 December 2012

  • Series ISSN: 0893-3405

  • Edition Number: 1

  • Number of Pages: XIX, 158

  • Topics: Circuits and Systems, Electrical Engineering

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