Writing Testbenches: Functional Verification of HDL Models

1. Front Matter

   Pages i-xxx

   PDF

2. What is Verification?

   • Janick Bergeron

   Pages 1-24

3. Verification Tools

   • Janick Bergeron

   Pages 25-84

4. The Verification Plan

   • Janick Bergeron

   Pages 85-120

5. High-Level Modeling

   • Janick Bergeron

   Pages 121-228

6. Stimulus and Response

   • Janick Bergeron

   Pages 229-318

7. Architecting Testbenches

   • Janick Bergeron

   Pages 319-374

8. Simulation Management

   • Janick Bergeron

   Pages 375-428

9. Back Matter

   Pages 429-478

   PDF

mental improvements during the same period. What is clearly needed in verification techniques and technology is the equivalent of a synthesis productivity breakthrough. In the second edition of Writing Testbenches, Bergeron raises the verification level of abstraction by introducing coverage-driven constrained-random transaction-level self-checking testbenches­ all made possible through the introduction of hardware verification languages (HVLs), such as e from Verisity and OpenVera from Synopsys. The state-of-art methodologies described in Writing Test­ benches will contribute greatly to the much-needed equivalent of a synthesis breakthrough in verification productivity. I not only highly recommend this book, but also I think it should be required reading by anyone involved in design and verification of today's ASIC, SoCs and systems. Harry Foster Chief Architect Verplex Systems, Inc. xviii Writing Testbenches: Functional Verification of HDL Models PREFACE If you survey hardware design groups, you will learn that between 60% and 80% of their effort is now dedicated to verification.

• Factor
• Hardware
• Hardwarebeschreibungssprache
• Interface
• Rack
• Simulation
• SoC
• VHDL
• Verilog
• hardware verification
• integrated circuit
• model
• modeling
• programming
• system on chip (SoC)

"Brilliant. Janick Bergeron has built on his ground-breaking first version of Writing Testbenches in this second edition..."
(Grant Martin, Fellow, Cadence Berkeley Labs)
"In the latest edition, Mr. Bergeron continues to keep pace with the industry while providing world-class solutions to the verification problem..."
(Chris Macinonski, Senior Engineer, Qualis Design Corp.)
"Many companies out there now owe their current verification methodologies to this book. From it they have learned the secrets of efficiency, effectiveness and re-use as they apply to verification..."
(Brian Bailey, Chief Technologist, Mentor Graphics Corp.)
"A must have bible for understanding verification issues and techniques with HDLs and HVLs, and for writing effective, readable and reusable testbenches within a best-in-class verification process."
(Ben Cohen, VhdlCohen Training)

• Qualis Design Corporation, USA

  Janick Bergeron

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