Concurrent data structures simplify the development of concurrent programs by encapsulating commonly used mechanisms for synchronization and commu nication into data structures. This thesis develops a notation for describing concurrent data structures, presents examples of concurrent data structures, and describes an architecture to support concurrent data structures. Concurrent Smalltalk (CST), a derivative of Smalltalk-80 with extensions for concurrency, is developed to describe concurrent data structures. CST allows the programmer to specify objects that are distributed over the nodes of a concurrent computer. These distributed objects have many constituent objects and thus can process many messages simultaneously. They are the foundation upon which concurrent data structures are built. The balanced cube is a concurrent data structure for ordered sets. The set is distributed by a balanced recursive partition that maps to the subcubes of a binary 7lrcube using a Gray code. A search algorithm, VW search, based on the distance properties of the Gray code, searches a balanced cube in O(log N) time. Because it does not have the root bottleneck that limits all tree-based data structures to 0(1) concurrency, the balanced cube achieves 0C.:N) con currency. Considering graphs as concurrent data structures, graph algorithms are pre sented for the shortest path problem, the max-flow problem, and graph parti tioning. These algorithms introduce new synchronization techniques to achieve better performance than existing algorithms.

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Authors and Affiliations

Massachusetts Institute of Technology, USA

William J. Dally

Bibliographic Information

Book Title: A VLSI Architecture for Concurrent Data Structures
Authors: William J. Dally
Series Title: The Springer International Series in Engineering and Computer Science
DOI: https://doi.org/10.1007/978-1-4613-1995-5
Publisher: Springer New York, NY
eBook Packages: Springer Book Archive
Copyright Information: Kluwer Academic Publishers 1987
Hardcover ISBN: 978-0-89838-235-8Published: 30 September 1987
Softcover ISBN: 978-1-4612-9191-6Published: 01 November 2011
eBook ISBN: 978-1-4613-1995-5Published: 06 December 2012
Series ISSN: 0893-3405
Edition Number: 1
Number of Pages: XX, 244
Topics: Circuits and Systems, Processor Architectures, Electrical Engineering

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Table of contents (6 chapters)

Front Matter

Introduction

Concurrent Smalltalk

The Balanced Cube

Graph Algorithms

Architecture

Conclusion

Back Matter

About this book