Overview
- Authors:
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Balsha R. Stanisic
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IBM, Rochester, USA
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Rob A. Rutenbar
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Carnegie Mellon University, USA
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L. Richard Carley
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Carnegie Mellon University, USA
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Table of contents (6 chapters)
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- Balsha R. Stanisic, Rob A. Rutenbar, L. Richard Carley
Pages 1-11
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- Balsha R. Stanisic, Rob A. Rutenbar, L. Richard Carley
Pages 13-37
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- Balsha R. Stanisic, Rob A. Rutenbar, L. Richard Carley
Pages 39-81
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- Balsha R. Stanisic, Rob A. Rutenbar, L. Richard Carley
Pages 83-120
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- Balsha R. Stanisic, Rob A. Rutenbar, L. Richard Carley
Pages 121-175
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- Balsha R. Stanisic, Rob A. Rutenbar, L. Richard Carley
Pages 177-182
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Back Matter
Pages 183-207
About this book
In the early days of VLSI, the design of the power distribution for an integrated cir cuit was rather simple. Power distribution --the design of the geometric topology for the network of wires that connect the various power supplies, the widths of the indi vidual segments for each of these wires, the number and location of the power I/O pins around the periphery of the chip --was simple because the chips were simpler. Few available wiring layers forced floorplans that allowed simple, planar (non-over lapping) power networks. Lower speeds and circuit density made the choice of the wire widths easier: we made them just fat enough to avoid resistive voltage drops due to switching currents in the supply network. And we just didn't need enormous num bers of power and ground pins on the package for the chips to work. It's not so simple any more. Increased integration has forced us to focus on reliability concerns such as metal elec tromigration, which affects wire sizing decisions in the power network. Extra metal layers have allowed more flexibility in the topological layout of the power networks.
