Overview
Access this book
Tax calculation will be finalised at checkout
Other ways to access
Table of contents (14 chapters)
-
TLB Consistency and Virtual Caches
-
Simulation and Performance Studies — Cache Coherence
-
Cache Coherence Protocols
-
Software Cache Coherence Schemes
Keywords
About this book
Editors and Affiliations
Bibliographic Information
Book Title: Cache and Interconnect Architectures in Multiprocessors
Editors: Michel Dubois, Shreekant S. Thakkar
DOI: https://doi.org/10.1007/978-1-4613-1537-7
Publisher: Springer New York, NY
-
eBook Packages: Springer Book Archive
Copyright Information: Kluwer Academic Publishers 1990
Hardcover ISBN: 978-0-7923-9074-9Published: 31 July 1990
Softcover ISBN: 978-1-4612-8824-4Published: 19 September 2011
eBook ISBN: 978-1-4613-1537-7Published: 06 December 2012
Edition Number: 1
Number of Pages: XIV, 277
Topics: Processor Architectures