Overview
Part of the book series: The Springer International Series in Engineering and Computer Science (SECS, volume 358)
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Table of contents (9 chapters)
Keywords
About this book
The general purpose parallel computer is an elusive goal. Multithreaded processors have emerged as a promising solution to this conundrum by forming some amalgam of the commonplace control-flow (von Neumann) processor model with the more exotic data-flow approach. This new processor model offers many exciting possibilities and there is much research to be performed to make this technology widespread.
Multithreaded processors utilize the simple and efficient sequential execution technique of control-flow, and also data-flow like concurrency primitives. This supports the conceptually simple but powerful idea of rescheduling rather than blocking when waiting for data, e.g. from large and distributed memories, thereby tolerating long data transmission latencies. This makes multiprocessing far more efficient because the cost of moving data between distributed memories and processors can be hidden by other activity. The same hardware mechanisms may also be used to synchronize interprocess communications to awaiting threads, thereby alleviating operating system overheads.
Supporting synchronization and scheduling mechanisms in hardware naturally adds complexity. Consequently, existing multithreaded processor designs have tended to make incremental changes to existing control-flow processor designs to resolve some problems but not others.
Multithreaded Processor Design serves as an excellent reference source and is suitable as a text for advanced courses in computer architecture dealing with the subject.
Authors and Affiliations
Bibliographic Information
Book Title: Multithreaded Processor Design
Authors: Simon W. Moore
Series Title: The Springer International Series in Engineering and Computer Science
DOI: https://doi.org/10.1007/978-1-4613-1383-0
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Kluwer Academic Publishers 1996
Hardcover ISBN: 978-0-7923-9718-2Published: 30 April 1996
Softcover ISBN: 978-1-4612-8598-4Published: 26 September 2011
eBook ISBN: 978-1-4613-1383-0Published: 06 December 2012
Series ISSN: 0893-3405
Edition Number: 1
Number of Pages: XVIII, 142
Topics: Processor Architectures