Overview
- Provides overview of various, existing homogeneous/heterogeneous architectures, cache and memory structures, on-chip interconnects, etc. and explains why current programming models won’t scale when these architectures are scaled to meet the needs of hundreds and thousands of processor cores
- Analyzes emerging hardware architectures and their benefits
- Explains challenges and limitations faced by current operating systems and introduces novel solutions, e.g., to resource management and scheduling
- Explains key concepts in many-core middleware, such as shared memory vs message passing approaches, data vs computation movement, and hint-based vs application driven assignment of tasks
- Explores the most promising programming models, focusing on scalability
- Includes supplementary material: sn.pub/extras
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Table of contents (10 chapters)
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Front Matter
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Back Matter
Keywords
About this book
This book presents new concepts, techniques and promising programming models for designing software for chips with "many" (hundreds to thousands) processor cores. Given the scale of parallelism inherent to these chips, software designers face new challenges in terms of operating systems, middleware and applications. This will serve as an invaluable, single-source reference to the state-of-the-art in programming many-core chips. Coverage includes many-core architectures, operating systems, middleware, and programming models.
Authors and Affiliations
Bibliographic Information
Book Title: Programming Many-Core Chips
Authors: András Vajda
DOI: https://doi.org/10.1007/978-1-4419-9739-5
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science +Business Media, LLC 2011
Hardcover ISBN: 978-1-4419-9738-8Published: 21 June 2011
Softcover ISBN: 978-1-4899-9169-0Published: 01 October 2014
eBook ISBN: 978-1-4419-9739-5Published: 10 June 2011
Edition Number: 1
Number of Pages: XII, 228
Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design