Overview
- Describes in detail the synthesis of logic functions using memories
- Includes a look-up tables (LUT) cascade as a new architecture for logic synthesis
- Shows logic design methods for index generation functions
- Introduces C-measure, which specifies the complexity of Boolean functions
- Presents hash-based design methods, which efficiently synthesize index generation functions by pairs of smaller memories and can be applied to IP address tables, packet filtering, terminal access controllers, memory patch circuits, virus scanning circuits, fault map of memories, and pattern matching
- Includes supplementary material: sn.pub/extras
Access this book
Tax calculation will be finalised at checkout
Other ways to access
Table of contents (13 chapters)
-
Front Matter
-
Back Matter
Keywords
About this book
This book describes the synthesis of logic functions using memories. It is useful to design field programmable gate arrays (FPGAs) that contain both small-scale memories, called look-up tables (LUTs), and medium-scale memories, called embedded memories. This is a valuable reference for both FPGA system designers and CAD tool developers, concerned with logic synthesis for FPGAs.
Authors and Affiliations
Bibliographic Information
Book Title: Memory-Based Logic Synthesis
Authors: Tsutomu Sasao
DOI: https://doi.org/10.1007/978-1-4419-8104-2
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media, LLC 2011
Hardcover ISBN: 978-1-4419-8103-5Published: 08 March 2011
Softcover ISBN: 978-1-4899-9153-9Published: 28 September 2014
eBook ISBN: 978-1-4419-8104-2Published: 01 March 2011
Edition Number: 1
Number of Pages: XII, 189
Topics: Energy, general, Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design