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Power Distribution Networks with On-Chip Decoupling Capacitors

  • Book
  • © 2011

Overview

  • Describes power distribution systems and related design problems, including both circuit models and design techniques to allocate on-chip decoupling capacitors
  • Details effects of inductance on impedance characteristics of on-chip power distribution grids
  • Includes new material on inductance models for interdigitated structures, design strategies for multi-layer power grid networks, and advanced algorithms for computational power grid analysis
  • Includes supplementary material: sn.pub/extras

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Table of contents (31 chapters)

  1. General Background

  2. Design of Power Systems

  3. Noise in Power Distribution Networks

Keywords

About this book

This book describes methods for distributing power in high speed, high complexity integrated circuits with power levels exceeding many tens of watts and power supplies below a volt. It provides a broad and cohesive treatment of power distribution systems and related design problems, including both circuit network models and design techniques for on-chip decoupling capacitors, providing insight and intuition into the behavior and design of on-chip power distribution systems.

Organized into subareas to provide a more intuitive flow to the reader, this second edition adds more than a hundred pages of new content, including inductance models for interdigitated structures, design strategies for multi-layer power grids, advanced methods for efficient power grid design and analysis, and methodologies for simultaneously placing on-chip multiple power supplies and decoupling capacitors. The emphasis of this additional material is on managing the complexity of on-chip power distribution networks.

Authors and Affiliations

  • University of Rochester, Rochester, USA

    Renatas Jakushokas, Selçuk Köse, Eby G. Friedman

  • Qualcomm Incorporated, San Diego, USA

    Mikhail Popovich

  • Intel Corporation, Hillsboro, USA

    Andrey V. Mezhiba

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