Low-Power Variation-Tolerant Design in Nanometer Silicon

1. Front Matter

   Pages i-xv

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2. Physics of Power Dissipations and Parameter Variations

   1. Front Matter

      Pages 1-1

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   2. Variations: Sources and Characterization

      • Aditya Bansal, Rahul M. Rao

      Pages 3-39

   3. Power Dissipation

      • Wei Zhang, James Williamson, Li Shang

      Pages 41-80

3. Circuit-Level Design Solutions

   1. Front Matter

      Pages 81-81

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4. Circuit Level Design Solutions

   1. Effect of Variations and Variation Tolerance in Logic Circuits

      • Swaroop Ghosh

      Pages 83-108

   2. Statistical Design of Integrated Circuits

      • Sachin S. Sapatnekar

      Pages 109-149

   3. Low-Power and Variation-Tolerant Memory Design

      • Hamid Mahmoodi

      Pages 151-183

   4. Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges

      • Bipul C. Paul, Arijit Raychowdhury

      Pages 185-207

5. System-Level Design Solutions

   1. Front Matter

      Pages 209-209

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6. System Level Design Solutions

   1. Variation-Tolerant Microprocessor Architecture at Low Power

      • Meeta S. Gupta, Pradip Bose

      Pages 211-247

   2. Low-Power and Variation-Tolerant Application-Specific System Design

      • Georgios Karakonstantis, Kaushik Roy

      Pages 249-292

   3. Low-Power Adaptive Mixed Signal/RF Circuits and Systems and Self-Healing Solutions

      • Shreyas Sen, Vishwanath Natarajan, Abhijit Chatterjee

      Pages 293-333

7. Low-Power and Robust Reconfigurable Computing

   1. Front Matter

      Pages 335-335

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   2. Low-Power Techniques for FPGAs

      • Nikil Mehta, André DeHon

      Pages 337-363

   3. Variation and Aging Tolerance in FPGAs

      • Nikil Mehta, André DeHon

      Pages 365-380

   4. Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging

      • Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon

      Pages 381-432

8. Back Matter

   Pages 433-440

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Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.

• DFM
• Design for Manufacturing
• EDA
• Electronic Design Automation
• Integrated Circuit Design
• Low Power IC Design
• Low Power Logic Design
• Low Power Memory Design
• Manufacturing Process Variation
• Nanometer IC Design
• Process Uncertainty
• Reliability
• Reliable IC Design
• Temperature-Aware Design

• Dept. Electrical Engineering &, Computer Science, Case Western Reserve University, Cleveland, USA

  Swarup Bhunia

• School of Electrical &, Computer Engineering, Georgia Institute of Technology, Atlanta, USA

  Saibal Mukhopadhyay

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