Skip to main content
SpringerLink
Log in
Book cover

Low-Power Variation-Tolerant Design in Nanometer Silicon

  • Book
  • © 2011

Overview

Editors:
  1. Swarup Bhunia

    1. Dept. Electrical Engineering &, Computer Science, Case Western Reserve University, Cleveland, USA

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  2. Saibal Mukhopadhyay

    1. School of Electrical &, Computer Engineering, Georgia Institute of Technology, Atlanta, USA

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  • Presents important challenges in nanometer scale integrated circuit design
  • Presents a holistic view of Low-Power Variation-Tolerant Design
  • Covers modeling, analysis and design methodology for low power and variation-tolerant logic circuits, memory and systems

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 84.99
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 139.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (12 chapters)

  1. Front Matter

    Pages i-xv
    Download chapter PDF

  2. Physics of Power Dissipations and Parameter Variations

    1. Front Matter

      Pages 1-1
      Download chapter PDF

    2. Variations: Sources and Characterization

      • Aditya Bansal, Rahul M. Rao
      Pages 3-39

    3. Power Dissipation

      • Wei Zhang, James Williamson, Li Shang
      Pages 41-80

  3. Circuit-Level Design Solutions

    1. Front Matter

      Pages 81-81
      Download chapter PDF

  4. Circuit Level Design Solutions

    1. Effect of Variations and Variation Tolerance in Logic Circuits

      • Swaroop Ghosh
      Pages 83-108

    2. Statistical Design of Integrated Circuits

      • Sachin S. Sapatnekar
      Pages 109-149

    3. Low-Power and Variation-Tolerant Memory Design

      • Hamid Mahmoodi
      Pages 151-183

    4. Digital Subthreshold for Ultra-Low Power Operation: Prospects and Challenges

      • Bipul C. Paul, Arijit Raychowdhury
      Pages 185-207

  5. System-Level Design Solutions

    1. Front Matter

      Pages 209-209
      Download chapter PDF

  6. System Level Design Solutions

    1. Variation-Tolerant Microprocessor Architecture at Low Power

      • Meeta S. Gupta, Pradip Bose
      Pages 211-247

    2. Low-Power and Variation-Tolerant Application-Specific System Design

      • Georgios Karakonstantis, Kaushik Roy
      Pages 249-292

    3. Low-Power Adaptive Mixed Signal/RF Circuits and Systems and Self-Healing Solutions

      • Shreyas Sen, Vishwanath Natarajan, Abhijit Chatterjee
      Pages 293-333

  7. Low-Power and Robust Reconfigurable Computing

    1. Front Matter

      Pages 335-335
      Download chapter PDF

    2. Low-Power Techniques for FPGAs

      • Nikil Mehta, André DeHon
      Pages 337-363

    3. Variation and Aging Tolerance in FPGAs

      • Nikil Mehta, André DeHon
      Pages 365-380

    4. Component-Specific Mapping for Low-Power Operation in the Presence of Variation and Aging

      • Benjamin Gojman, Nikil Mehta, Raphael Rubin, André DeHon
      Pages 381-432

  8. Back Matter

    Pages 433-440
    Download chapter PDF
Back to top

Keywords

About this book

Design considerations for low-power operations and robustness with respect to variations typically impose contradictory requirements. Low-power design techniques such as voltage scaling, dual-threshold assignment and gate sizing can have large negative impact on parametric yield under process variations. This book focuses on circuit/architectural design techniques for achieving low power operation under parameter variations. We consider both logic and memory design aspects and cover modeling and analysis, as well as design methodology to achieve simultaneously low power and variation tolerance, while minimizing design overhead. This book will discuss current industrial practices and emerging challenges at future technology nodes.

Editors and Affiliations

  • Dept. Electrical Engineering &, Computer Science, Case Western Reserve University, Cleveland, USA

    Swarup Bhunia

  • School of Electrical &, Computer Engineering, Georgia Institute of Technology, Atlanta, USA

    Saibal Mukhopadhyay

Bibliographic Information

  • Book Title: Low-Power Variation-Tolerant Design in Nanometer Silicon

  • Editors: Swarup Bhunia, Saibal Mukhopadhyay

  • DOI: https://doi.org/10.1007/978-1-4419-7418-1

  • Publisher: Springer New York, NY

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer Science+Business Media, LLC 2011

  • Hardcover ISBN: 978-1-4419-7417-4Published: 24 November 2010

  • Softcover ISBN: 978-1-4899-8157-8Published: 10 October 2014

  • eBook ISBN: 978-1-4419-7418-1Published: 10 November 2010

  • Edition Number: 1

  • Number of Pages: XV, 440

  • Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design

Publish with us

Policies and ethics

Back to top

Search

Navigation