Low Power Networks-on-Chip

1. Front Matter

   Pages i-xix

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2. Low-Level Design Techniques

   1. Front Matter

      Pages 1-1

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   2. Hybrid Circuit/Packet Switched Network for Energy Efficient on-Chip Interconnections

      • Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy, Shekhar Y. Borkar

      Pages 3-20

   3. Run-Time Power-Gating Techniques for Low-Power On-Chip Networks

      • Hiroki Matsutani, Michihiro Koibuchi, Hiroshi Nakamura, Hideharu Amano

      Pages 21-43

   4. Adaptive Voltage Control for Energy-Efficient NoC Links

      • Paul Ampadu, Bo Fu, David Wolpert, Qiaoyan Yu

      Pages 45-69

   5. Asynchronous Communications for NoCs

      • Stanislavs Golubcovs, Alex Yakovlev

      Pages 71-109

3. System-Level Design Techniques

   1. Front Matter

      Pages 111-111

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   2. Application-Specific Routing Algorithms for Low Power Network on Chip Design

      • Maurizio Palesi, Rickard Holsmark, Shashi Kumar, Vincenzo Catania

      Pages 113-150

   3. Adaptive Data Compression for Low-Power On-Chip Networks

      • Yuho Jin, Ki Hwan Yum, Eun Jung Kim

      Pages 151-174

   4. Latency-Constrained, Power-Optimized NoC Design for a 4G SoC: A Case Study

      • Rudy Beraha, Isask’har Walter, Israel Cidon, Avinoam Kolodny

      Pages 175-195

4. Future and Emerging Technologies

   1. Front Matter

      Pages 197-197

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   2. Design and Analysis of NoCs for Low-Power 2D and 3D SoCs

      • Ciprian Seiculescu, Srinivasan Murali, Luca Benini, Giovanni De Micheli

      Pages 199-222

   3. CMOS Nanophotonics: Technology, System Implications, and a CMP Case Study

      • Jung Ho Ahn, Raymond G. Beausoleil, Nathan Binkert, Al Davis, Marco Fiorentino, Norman P. Jouppi et al.

      Pages 223-254

   4. RF-Interconnect for Future Network-On-Chip

      • Sai-Wang Tam, Eran Socher, Mau-Chung Frank Chang, Jason Cong, Glenn D. Reinman

      Pages 255-280

5. Back Matter

   Pages 281-287

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In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

• Embedded Systems
• High Speed Interconnect
• Low Power Design
• Network on Chip
• On-Chip Communication Architectures
• System-on-Chip

• Dipto. Elettronica e Informazione (DEI), Politecnico di Milano, Milano, Italy

  Cristina Silvano, Gianluca Palermo

• NEC Laboratories America, Inc., Princeton, USA

  Marcello Lajolo

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