Skip to main content
SpringerLink
Log in
Book cover

Coupled Data Communication Techniques for High-Performance and Low-Power Computing

  • Book
  • © 2010

Overview

Editors:
  1. Ron Ho

    1. Sun Microsystems Laboratories, VLSI Research Group, Sun Microsystems, Inc., Menlo Park, USA

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  2. Robert Drost

    1. Sun Microsystems Laboratories, VLSI Research Group, Sun Microsystems, Inc., Menlo Park, USA

    View editor publications

    You can also search for this editor in PubMed   Google Scholar

  • Serves as a collection of the best-known-methods and ideas from leaders in the field.
  • Includes a carefully-selected set of discussions on the important issues, tradeoffs, and techniques in coupled data I/O.
  • Provides an overview of the circuits, architectures, and chip packaging for coupled data techniques.
  • Covers the new and emerging area of coupled data communication.
  • Includes supplementary material: sn.pub/extras

Part of the book series: Integrated Circuits and Systems (ICIR)

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (8 chapters)

  1. Front Matter

    Pages i-xvi
    Download chapter PDF

  2. Introduction

    1. Front Matter

      Pages 1-1
      Download chapter PDF

    2. Introduction to Coupled Data Technologies

      • Ron Ho, Robert Drost
      Pages 3-10

  3. Overview of 3D Technologies

    1. Front Matter

      Pages 12-12
      Download chapter PDF

    2. Power delivery, signaling and cooling for 2D and 3D integrated systems

      • Muhannad Bakir, Gang Huang, Bing Dang
      Pages 13-48

  4. Coupled Data Technologies

    1. Front Matter

      Pages 50-50
      Download chapter PDF

    2. Capacitive Coupled Communication

      • David Hopkins, Alex Chow, Frankie Liu, Dinesh D. Patil, Hans Eberle
      Pages 51-77

    3. Inductive Coupled Communications

      • Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda
      Pages 79-125

    4. Use of AC Coupled Interconnect in Contactless Packaging

      • Paul Franzon
      Pages 127-153

  5. Enabling Coupled Data Technologies

    1. Front Matter

      Pages 156-156
      Download chapter PDF

    2. Aligning chips face-to-face for dense capacitive communication

      • John E. Cunningham, Ashok V. Krishnamoorthy, Ivan Shubin, James G. Mitchell, Xuezhe Zheng
      Pages 157-175

  6. Extending Data Coupling Technologies

    1. Front Matter

      Pages 178-178
      Download chapter PDF

  7. Extending Data Coupling Technologies

    1. Delivering On-chip Bandwidth Off-chip and Out-of-box with Proximity and Optical Communication

      • Ashok V. Krishnamoorthy, Jon Lexau, Xuezhe Zheng, John E. Cunningham
      Pages 179-192

    2. AC Coupled Wireless Power Delivery

      • Makoto Takamiya, Kohei Onizuka, Takayasu Sakurai
      Pages 193-204

  8. Back Matter

    Pages 205-206
    Download chapter PDF
Back to top

Keywords

About this book

Wafer-scale integration has long been the dream of system designers. Instead of chopping a wafer into a few hundred or a few thousand chips, one would just connect the circuits on the entire wafer. What an enormous capability wafer-scale integration would offer: all those millions of circuits connected by high-speed on-chip wires. Unfortunately, the best known optical systems can provide suitably ?ne resolution only over an area much smaller than a whole wafer. There is no known way to pattern a whole wafer with transistors and wires small enough for modern circuits. Statistical defects present a ?rmer barrier to wafer-scale integration. Flaws appear regularly in integrated circuits; the larger the circuit area, the more probable there is a ?aw. If such ?aws were the result only of dust one might reduce their numbers, but ?aws are also the inevitable result of small scale. Each feature on a modern integrated circuit is carved out by only a small number of photons in the lithographic process. Each transistor gets its electrical properties from only a small number of impurity atoms in its tiny area. Inevitably, the quantized nature of light and the atomic nature of matter produce statistical variations in both the number of photons de?ning each tiny shape and the number of atoms providing the electrical behavior of tiny transistors. No known way exists to eliminate such statistical variation, nor may any be possible.

Editors and Affiliations

  • Sun Microsystems Laboratories, VLSI Research Group, Sun Microsystems, Inc., Menlo Park, USA

    Ron Ho, Robert Drost

Bibliographic Information

Publish with us

Policies and ethics

Back to top

Search

Navigation