Low Power Hardware Synthesis from Concurrent Action-Oriented Specifications

1. Front Matter

   Pages i-xxix

   PDF

2. Introduction

   • Gaurav Singh, Sandeep K. Shukla

   Pages 1-12

3. Related Work

   • Gaurav Singh, Sandeep K. Shukla

   Pages 13-24

4. Background

   • Gaurav Singh, Sandeep K. Shukla

   Pages 25-34

5. Low-Power Problem Formalization

   • Gaurav Singh, Sandeep K. Shukla

   Pages 35-43

6. Heuristics for Power Savings

   • Gaurav Singh, Sandeep K. Shukla

   Pages 45-64

7. Complexity Analysis of Scheduling in CAOS-Based Synthesis

   • Gaurav Singh, Sandeep K. Shukla

   Pages 65-82

8. Dynamic Power Optimizations

   • Gaurav Singh, Sandeep K. Shukla

   Pages 83-101

9. Peak Power Optimizations

   • Gaurav Singh, Sandeep K. Shukla

   Pages 103-113

10. Verifying Peak Power Optimizations Using SPIN Model Checker

    • Gaurav Singh, Sandeep K. Shukla

    Pages 115-139

11. Epilogue

    • Gaurav Singh, Sandeep K. Shukla

    Pages 141-143

12. Back Matter

    Pages 145-153

    PDF

Human lives are getting increasingly entangled with technology, especially comp- ing and electronics. At each step we take, especially in a developing world, we are dependent on various gadgets such as cell phones, handheld PDAs, netbooks, me- cal prosthetic devices, and medical measurement devices (e.g., blood pressure m- itors, glucometers). Two important design constraints for such consumer electronics are their form factor and battery life. This translates to the requirements of reduction in the die area and reduced power consumption for the semiconductor chips that go inside these gadgets. Performance is also important, as increasingly sophisticated applications run on these devices, and many of them require fast response time. The form factor of such electronics goods depends not only on the overall area of the chips inside them but also on the packaging, which depends on thermal ch- acteristics. Thermal characteristics in turn depend on peak power signature of the chips. As a result, while the overall energy usage reduction increases battery life, peak power reduction in?uences the form factor. One more important aspect of these electronic equipments is that every 6 months or so, a newer feature needs to be added to keep ahead of the market competition, and hence new designs have to be completed with these new features, better form factor, battery life, and performance every few months. This extreme pressure on the time to market is another force that drives the innovations in design automation of semiconductor chips.

• CAOS
• Circuit Design
• Concurrent Action-Oriented Specifications
• Embedded Systems
• Formal Verification
• High-level Synthesis
• Low-power Design
• integrated circuit
• model

• Intel Corporation, Austin, USA

  Gaurav Singh

• Bradley Dept. Electrical &, Computer Engineering, Virginia Tech, Blacksburg, USA

  Sandeep K. Shukla

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