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Table of contents (11 chapters)
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Front Matter
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Back Matter
Keywords
About this book
VHDL and logic synthesis tools provide very powerful capabilities for ASIC design, but are also very complex and represent a radical departure from traditional design methods. This situation has made it difficult to get started in using this technology for both designers and management, since a major learning effort and `culture' change is required. A Designer's Guide to VHDL Synthesis has been written to help design engineers and other professionals successfully make the transition to a design methodology based on VHDL and log synthesis instead of the more traditional schematic based approach. While there are a number of texts on the VHDL language and its use in simulation, little has been written from a designer's viewpoint on how to use VHDL and logic synthesis to design real ASIC systems. The material in this book is based on experience gained in successfully using these techniques for ASIC design and relies heavily on realistic examples to demonstrate the principles involved.
Authors and Affiliations
Bibliographic Information
Book Title: A Designer's Guide to VHDL Synthesis
Authors: Douglas E. Ott, Thomas J. Wilderotter
DOI: https://doi.org/10.1007/978-1-4757-2303-8
Publisher: Springer New York, NY
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eBook Packages: Springer Book Archive
Copyright Information: Springer-Verlag US 1994
Hardcover ISBN: 978-0-7923-9472-3Published: 30 June 1994
Softcover ISBN: 978-1-4419-5143-4Published: 03 December 2010
eBook ISBN: 978-1-4757-2303-8Published: 19 December 2013
Edition Number: 1
Number of Pages: XXVI, 306
Topics: Circuits and Systems, Electrical Engineering, Computer-Aided Engineering (CAD, CAE) and Design