Skip to main content
SpringerLink
Log in

Hardware Acceleration of EDA Algorithms

Custom ICs, FPGAs and GPUs

  • Book
  • © 2010

Overview

Authors:
  1. Kanupriya Gulati

    1. Coppell, U.S.A.

    View author publications

    You can also search for this author in PubMed   Google Scholar

  2. Sunil P. Khatri

    1. Dept. Electrical & Computer Engineering, Texas A & M University, College Station, U.S.A.

    View author publications

    You can also search for this author in PubMed   Google Scholar

  • Provides guidelines on whether to use GPUs or FPGAs when accelerating a given EDA algorithm, with validation by a concrete example implemented on both platforms
  • Demonstrates the acceleration of several popular EDA algorithms on GPUs, with speedups from 30X to 800X
  • Presents techniques in a way that the reader can use example algorithms presented to determine how best to accelerate their specific EDA algorithm
  • Discusses an automatic approach to generate GPU code, given regular uniprocessor code
  • Includes supplementary material: sn.pub/extras

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 84.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 149.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 109.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (12 chapters)

  1. Front Matter

    Pages i-xxii
    Download chapter PDF

  2. Introduction

    • Kanupriya Gulati, Sunil P. Khatri
    Pages 1-5

  3. Alternative Hardware Platforms

    1. Front Matter

      Pages 7-8
      Download chapter PDF

    2. Hardware Platforms

      • Kanupriya Gulati, Sunil P. Khatri
      Pages 9-22

    3. GPU Architecture and the CUDA Programming Model

      • Kanupriya Gulati, Sunil P. Khatri
      Pages 23-30

  4. Control-Dominated Category

    1. Front Matter

      Pages 31-32
      Download chapter PDF

  5. Control Dominated Category

    1. Accelerating Boolean Satisfiability on a Custom IC

      • Kanupriya Gulati, Sunil P. Khatri
      Pages 33-61

    2. Accelerating Boolean Satisfiability on an FPGA

      • Kanupriya Gulati, Sunil P. Khatri
      Pages 63-81

    3. Accelerating Boolean Satisfiability on a Graphics Processing Unit

      • Kanupriya Gulati, Sunil P. Khatri
      Pages 83-99

  6. Control Plus Data Parallel Applications

    1. Front Matter

      Pages 101-103
      Download chapter PDF

    2. Accelerating statistical static Timing Analysis Using Graphics Processors

      • Kanupriya Gulati, Sunil P. Khatri
      Pages 105-118

    3. Accelerating Fault Simulation Using Graphics Processors

      • Kanupriya Gulati, Sunil P. Khatri
      Pages 119-132

    4. Fault Table Generation Using Graphics Processors

      • Kanupriya Gulati, Sunil P. Khatri
      Pages 133-152

    5. Accelerating Circuit Simulation Using Graphics Processors

      • Kanupriya Gulati, Sunil P. Khatri
      Pages 153-165

  7. Automated Generation of GPU Code

    1. Front Matter

      Pages 167-167
      Download chapter PDF

    2. Automated Approach for Graphics Processor Based Software Acceleration

      • Kanupriya Gulati, Sunil P. Khatri
      Pages 169-180

    3. Conclusions

      • Kanupriya Gulati, Sunil P. Khatri
      Pages 181-187

  8. Back Matter

    Pages 189-192
    Download chapter PDF
Back to top

Keywords

About this book

Single-threaded software applications have ceased to see signi?cant gains in p- formance on a general-purpose CPU, even with further scaling in very large scale integration (VLSI) technology. This is a signi?cant problem for electronic design automation (EDA) applications, since the design complexity of VLSI integrated circuits (ICs) is continuously growing. In this research monograph, we evaluate custom ICs, ?eld-programmable gate arrays (FPGAs), and graphics processors as platforms for accelerating EDA algorithms, instead of the general-purpose sing- threaded CPU. We study applications which are used in key time-consuming steps of the VLSI design ?ow. Further, these applications also have different degrees of inherent parallelism in them. We study both control-dominated EDA applications and control plus data parallel EDA applications. We accelerate these applications on these different hardware platforms. We also present an automated approach for accelerating certain uniprocessor applications on a graphics processor. This monograph compares custom ICs, FPGAs, and graphics processing units (GPUs) as potential platforms to accelerate EDA algorithms. It also provides details of the programming model used for interfacing with the GPUs.

Authors and Affiliations

  • Coppell, U.S.A.

    Kanupriya Gulati

  • Dept. Electrical & Computer Engineering, Texas A & M University, College Station, U.S.A.

    Sunil P. Khatri

Bibliographic Information

  • Book Title: Hardware Acceleration of EDA Algorithms

  • Book Subtitle: Custom ICs, FPGAs and GPUs

  • Authors: Kanupriya Gulati, Sunil P. Khatri

  • DOI: https://doi.org/10.1007/978-1-4419-0944-2

  • Publisher: Springer New York, NY

  • eBook Packages: Engineering, Engineering (R0)

  • Copyright Information: Springer-Verlag US 2010

  • Hardcover ISBN: 978-1-4419-0943-5Published: 06 April 2010

  • Softcover ISBN: 978-1-4899-8333-6Published: 05 September 2014

  • eBook ISBN: 978-1-4419-0944-2Published: 11 March 2010

  • Edition Number: 1

  • Number of Pages: XXII, 192

  • Topics: Circuits and Systems, Computer-Aided Engineering (CAD, CAE) and Design

Publish with us

Policies and ethics

Back to top

Search

Navigation