Three-Dimensional Integrated Circuit Design

1. Front Matter

   Pages i-xii

   PDF

2. Introduction

   • Kerry Bernstein

   Pages 1-13

3. 3D Process Technology Considerations

   • Albert M. Young, Steven J. Koester

   Pages 15-32

4. Thermal and Power Delivery Challenges in 3D ICs

   • Pulkit Jain, Pingqiang Zhou, Chris H. Kim, Sachin S. Sapatnekar

   Pages 33-61

5. Thermal-Aware 3D Floorplan

   • Jason Cong, Yuchun Ma

   Pages 63-102

6. Thermal-Aware 3D Placement

   • Jason Cong, Guojie Luo

   Pages 103-144

7. Thermal Via Insertion and Thermally Aware Routing in 3D ICs

   • Sachin S. Sapatnekar

   Pages 145-160

8. Three-Dimensional Microprocessor Design

   • Gabriel H. Loh

   Pages 161-188

9. Three-Dimensional Network-on-Chip Architecture

   • Yuan Xie, Narayanan Vijaykrishnan, Chita Das

   Pages 189-217

10. PicoServer: Using 3D Stacking Technology to Build Energy Efficient Servers

    • Taeho Kgil, David Roberts, Trevor Mudge

    Pages 219-260

11. System-Level 3D IC Cost Analysis and Design Exploration

    • Xiangyu Dong, Yuan Xie

    Pages 261-280

12. Back Matter

    Pages 281-284

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We live in a time of great change. In the electronics world, the last several decades have seen unprecedented growth and advancement, described by Moore’s law. This observation stated that transistor density in integrated circuits doubles every 1. 5–2 years. This came with the simultaneous improvement of individual device perf- mance as well as the reduction of device power such that the total power of the resulting ICs remained under control. No trend remains constant forever, and this is unfortunately the case with Moore’s law. The trouble began a number of years ago when CMOS devices were no longer able to proceed along the classical scaling trends. Key device parameters such as gate oxide thickness were simply no longer able to scale. As a result, device o- state currents began to creep up at an alarming rate. These continuing problems with classical scaling have led to a leveling off of IC clock speeds to the range of several GHz. Of course, chips can be clocked higher but the thermal issues become unmanageable. This has led to the recent trend toward microprocessors with mul- ple cores, each running at a few GHz at the most. The goal is to continue improving performance via parallelism by adding more and more cores instead of increasing speed. The challenge here is to ensure that general purpose codes can be ef?ciently parallelized. There is another potential solution to the problem of how to improve CMOS technology performance: three-dimensional integrated circuits (3D ICs).

• FPGA
• automation
• circuit design
• design
• integrated circuit
• microprocessor
• network
• technology

• Dept. Computer Science & Engineering, Pennsylvania State University, University Park, U.S.A.

  Yuan Xie

• Dept. Computer Science, University of California, Los Angeles, Los Angeles, U.S.A.

  Jason Cong

• Institute of Technology, University of Minnesota, Minneapolis, U.S.A.

  Sachin Sapatnekar

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