Overview
- All high-speed ADC architectures (flash, two-step, folding and interpolation) covered in detail
- The performance parameters and trade-offs encountered in each of the ADC’s sub-blocks are analysed
- Most exhaustive study ever performed about averaging is presented
- Offset sampling techniques that yield a nearly offset free, high-speed, comparator are described
Part of the book series: Analog Circuits and Signal Processing (ACSP)
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Table of contents (6 chapters)
Keywords
About this book
Offset Reduction Techniques in High-Speed Analog-to-Digital Converters analyzes, describes the design, and presents test results of Analog-to-Digital Converters (ADCs) employing the three main high-speed architectures: flash, two-step flash and folding and interpolation. The advantages and limitations of each one are reviewed, and the techniques employed to improve their performance are discussed.
Authors and Affiliations
About the authors
Pedro Figueiredo received the degrees of Licenciado and Doutor (PhD) in Electrical and Computer Engineering in 1999 and 2006, respectively, from the Instituto Superior Técnico (IST), Lisbon, Portugal. From 1997 to 1999, he was with the Analog and Mixed-Mode Circuits Group in the Institute for Systems and Computer Engineering (INESC), Lisbon, Portugal, where he worked on low-noise logic families and high-speed Analog-to-Digital Converters.
In 1999, he joined Chipidea - Microelectrónica, where he currently leads the group responsible for the design of Analog-to-Digital Converters. His main research interests are in the area of analog and mixed-signal circuits, with emphasis on high-speed data conversion and design automation. He has 10 publications in international journals and conferences.
João Vital received the degrees of Licenciado, Mestre and Doutor (PhD) in Electrical and Computer Engineering in 1986, 1990 and 1994, respectively, all from the Instituto Superior Técnico (IST), Lisboa, Portugal. He is a Co-founder of Chipidea - Microelectronica in 1997, and currently serves as Vice-President of Data Conversion, leading the Data Conversion Solutions Division of Chipidea to provide competitive solutions towards the demanding markets of Broadband Wireless Communications and Video. His main scientific interests are in the area of analog and mixed-signal integrated-circuit design, with a focus on data conversion. He developed research work in the University of Pavia, Italy, in the University of California - Los Angeles, USA, and in the Oregon State University, USA, also in 1990. He has over 50 publications in international journals, book chapters and conferences and is a co-holder of an European and US Patent filed by British Telecom.
Bibliographic Information
Book Title: Offset Reduction Techniques in High-Speed Analog-to-Digital Converters
Book Subtitle: Analysis, Design and Tradeoffs
Authors: Pedro M. Figueiredo, JoÃo C. Vital
Series Title: Analog Circuits and Signal Processing
DOI: https://doi.org/10.1007/978-1-4020-9716-4
Publisher: Springer Dordrecht
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media B.V. 2009
Hardcover ISBN: 978-1-4020-9715-7Published: 09 March 2009
Softcover ISBN: 978-90-481-8192-6Published: 28 October 2010
eBook ISBN: 978-1-4020-9716-4Published: 10 March 2009
Series ISSN: 1872-082X
Series E-ISSN: 2197-1854
Edition Number: 1
Number of Pages: XX, 382
Topics: Circuits and Systems, Input/Output and Data Communications