Overview
- Implementation detail of three state-of-the-art low-power high-performance ADC and clock multiplier PLL designs using unique architectures
- Concise and graphical explanation of key points in ADC/PLL design at both architecture and circuit level
- Theory backed by extensive measurement results from actual silicon
Part of the book series: Analog Circuits and Signal Processing (ACSP)
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Table of contents (5 chapters)
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Front Matter
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Back Matter
Keywords
About this book
Low-Power High-Speed ADCs for Nanometer CMOS Integration is about the design and implementation of ADC in nanometer CMOS processes that achieve lower power consumption for a given speed and resolution than previous designs, through architectural and circuit innovations that take advantage of unique features of nanometer CMOS processes. A phase lock loop (PLL) clock multiplier has also been designed using new circuit techniques and successfully tested.
1) A 1.2V, 52mW, 210MS/s 10-bit two-step ADC in 130nm CMOS occupying 0.38mm2. Using offset canceling comparators and capacitor networks implemented with small value interconnect capacitors to replace resistor ladder/multiplexer in conventional sub-ranging ADCs, it achieves 74dB SFDR for 10MHz and 71dB SFDR for 100MHz input.
2) A 32mW, 1.25GS/s 6-bit ADC with 2.5GHz internal clock in 130nm CMOS. A new type of architecture that combines flash and SAR enables the lowest power consumption, 6-bit >1GS/s ADC reported to date. This design can be a drop-in replacement for existing flash ADCs since it does require any post-processing or calibration step and has the same latency as flash.
3) A 0.4ps-rms-jitter (integrated from 3kHz to 300MHz offset for >2.5GHz) 1-3GHz tunable, phase-noise programmable clock-multiplier PLL for generating sampling clock to the SAR ADC. A new loop filter structure enables phase error preamplification to lower PLL in-band noise without increasing loop filter capacitor size.
Authors and Affiliations
Bibliographic Information
Book Title: Low-Power High-Speed ADCs for Nanometer CMOS Integration
Authors: Zhiheng Cao, Shouli Yan
Series Title: Analog Circuits and Signal Processing
DOI: https://doi.org/10.1007/978-1-4020-8450-8
Publisher: Springer Dordrecht
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media B.V. 2008
Hardcover ISBN: 978-1-4020-8449-2Published: 08 July 2008
Softcover ISBN: 978-90-481-7885-8Published: 22 November 2010
eBook ISBN: 978-1-4020-8450-8Published: 15 July 2008
Series ISSN: 1872-082X
Series E-ISSN: 2197-1854
Edition Number: 1
Number of Pages: XIII, 95
Topics: Circuits and Systems, Energy Systems, Energy, general