Overview
- Explores problems in the design of fully-integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors
- Comprehensive coverage includes summary chapters on circuit theory as well as feedback control theory
- Discussion includes PLL analysis using continuous-time as well as discrete-time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior
- Includes numerous real world applications as well as useful rules-of-thumb for design at the system, architectural and circuit levels
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Table of contents (9 chapters)
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Front Matter
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Back Matter
Keywords
About this book
This book examines the issue of design of fully integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined. This includes sigma-delta fractional-N PLLs, Direct Digital Synthesis (DDS) techniques and non-conventional uses of PLLs. Design for test (DFT) issues as they arise in PLLs are then discussed. This includes methods of accurately measuring jitter and built-in-self-test (BIST) techniques for PLLs.
About the author
Amr M. Fahim received his B.A.Sc, M.A.Sc, and Ph.D degrees from the University of Waterloo in Computer Engineering in 1996 and Electrical Engineering in 1997 and 2000, respectively. In 2000 he joined Qualcomm Inc., where he is currently working on the development of mixed-signal designs. He is the author of over 20 papers and 5 patents in this area, and has been a reviewer for the IEEE Journal of Solid-State Circuits and IEEE Transactions on Circuits and Systems II.
Bibliographic Information
Book Title: Clock Generators for SOC Processors
Book Subtitle: Circuits and Architectures
Authors: Amr M. Fahim
DOI: https://doi.org/10.1007/b117041
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer-Verlag US 2005
Hardcover ISBN: 978-1-4020-8079-1Published: 24 June 2005
Softcover ISBN: 978-1-4419-5470-1Published: 05 November 2010
eBook ISBN: 978-1-4020-8080-7Published: 06 December 2005
Edition Number: 1
Number of Pages: XVIII, 246
Number of Illustrations: 213 b/w illustrations