Skip to main content
SpringerLink
Log in

Advanced Verification Techniques

A SystemC Based Approach for Successful Tapeout

  • Book
  • © 2004

Overview

Authors:
  1. Leena Singh

    1. Azanda Network Devices, USA

    View author publications

    You can also search for this author in PubMed   Google Scholar

  2. Leonard Drucker

    1. Cadence Design Systems Inc., USA

    View author publications

    You can also search for this author in PubMed   Google Scholar

  3. Neyaz Khan

    1. Cadence Design Systems Inc., USA

    View author publications

    You can also search for this author in PubMed   Google Scholar

  • Covers various processes followed for effective and efficient functional verification that guarantees first pass silicon success
  • Shows how SystemC and SCV can be applied to a variety of advanced design & verification tasks
  • Includes supplementary material: sn.pub/extras

  • 3221 Accesses

This is a preview of subscription content, log in via an institution to check access.

Access this book

Log in via an institution
eBook USD 129.00
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 169.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info
Hardcover Book USD 169.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access

Licence this eBook for your library

Institutional subscriptions

Table of contents (10 chapters)

  1. Front Matter

    Pages i-xviii
    Download chapter PDF

  2. Introduction

    Pages 1-16

  3. Verification Process

    Pages 17-43

  4. Using SCV for Verification

    Pages 45-64

  5. Functional Verification Testplan

    Pages 65-93

  6. Testbench Concepts using SystemC

    Pages 95-147

  7. Verification Methodology

    Pages 149-210

  8. Regression/Setup and Run

    Pages 211-231

  9. Functional Coverage

    Pages 233-250

  10. Dynamic Memory Modeling

    Pages 251-274

  11. Post Synthesis Gate Simulation

    Pages 275-295

  12. Back Matter

    Pages 297-376
    Download chapter PDF
Back to top

Keywords

About this book

"As chip size and complexity continues to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages.  Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks."
                                                                                     - Stuart Swan

Reviews

"As chip size and complexity continue to grow exponentially, the challenges of functional verification are becoming a critical issue in the electronics industry. It is now commonly heard that logical errors missed during functional verification are the most common cause of chip re-spins, and that the costs associated with functional verification are now outweighing the costs of chip design. To cope with these challenges engineers are increasingly relying on new design and verification methodologies and languages. Transaction-based design and verification, constrained random stimulus generation, functional coverage analysis, and assertion-based verification are all techniques that advanced design and verification teams routinely use today. Engineers are also increasingly turning to design and verification models based on C/C++ and SystemC in order to build more abstract, higher performance hardware and software models and to escape the limitations of RTL HDLs. This new book, Advanced Verification Techniques, provides specific guidance for these advanced verification techniques. The book includes realistic examples and shows how SystemC and SCV can be applied to a variety of advanced design and verification tasks."
(Stuart Swan)

Authors and Affiliations

  • Azanda Network Devices, USA

    Leena Singh

  • Cadence Design Systems Inc., USA

    Leonard Drucker, Neyaz Khan

Bibliographic Information

  • Book Title: Advanced Verification Techniques

  • Book Subtitle: A SystemC Based Approach for Successful Tapeout

  • Authors: Leena Singh, Leonard Drucker, Neyaz Khan

  • DOI: https://doi.org/10.1007/b105272

  • Publisher: Springer New York, NY

  • eBook Packages: Springer Book Archive

  • Copyright Information: Springer Science+Business Media New York 2004

  • Hardcover ISBN: 978-1-4020-7672-5Published: 08 June 2004

  • Softcover ISBN: 978-1-4419-5409-1Published: 07 December 2010

  • eBook ISBN: 978-1-4020-8029-6Published: 08 May 2007

  • Edition Number: 1

  • Number of Pages: XVIII, 376

  • Topics: Circuits and Systems, Electrical Engineering, Computer-Aided Engineering (CAD, CAE) and Design

Publish with us

Policies and ethics

Back to top

Search

Navigation