Interconnect-Centric Design for Advanced SOC and NOC

1. Front Matter

   Pages i-vii

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2. Physical and Electrical Issues

   1. Front Matter

      Pages 1-1

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   2. System-on-Chip-Challenges in the Deep-Sub-Micron Era

      • Jan M. Rabaey

      Pages 3-24

   3. Wires as Interconnects

      • Li-Rong Zheng, Hannu Tenhunen

      Pages 25-54

   4. Global Interconnect Analysis

      • Tero Nurmi, Jian Liu, Dinesh Pamunuwa, Tapani Ahonen, Li-Rong Zheng, Jouni Isoaho et al.

      Pages 55-84

   5. Design Methodologies for on-Chip Inductive Interconnect

      • Magdy A. El-Moursy, Eby G. Friedman

      Pages 85-124

   6. Clock Distribution for High Performance Designs

      • Stefan Rusu

      Pages 125-152

3. Logical and Architectural Issues

   1. Front Matter

      Pages 153-153

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   2. Error-Tolerant Interconnect Schemes

      • Heiko Zimmer, Axel Jantsch

      Pages 155-176

   3. Power Reduction Coding for Buses

      • Paul P. Sotiriadis

      Pages 177-205

   4. Bus Structures in Network-on-Chips

      • Vesa Lahtinen, Erno Salminen, Kimmo Kuusilinna, Timo D. Hämäläinen

      Pages 207-230

   5. From Buses to Networks

      • David Sigüuenza-Tortosa, Jari Nurmi

      Pages 231-251

   6. Arbitration and Routing Schemes for on-Chip Packet Networks

      • Heikki Kariniemi, Jari Nurmi

      Pages 253-282

4. Design Methodology and Tools

   1. Front Matter

      Pages 283-283

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   2. Self-Timed Approach for Noise Reduction in NoC Reduction in NoC

      • Pasi Liljeberg, Johanna Tuominen, Sampo Tuuna, Juha Plosila, Jouni Isoaho

      Pages 285-313

   3. Formal Communication Modeling and Refinement

      • Juha Plosila, Tiberiu Seceleanu, Kaisa Sere

      Pages 315-340

   4. Network-Centric System-Level Model for Multiprocessor Soc Simulation

      • Jan Madsen, 1Shankar Mahadevan, Kashif Virk

      Pages 341-365

   5. Socket-Based Design Using Decoupled Interconnects

      • Drew Wingard

      Pages 367-396

5. Application Cases

   1. Front Matter

      Pages 397-397

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   2. Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV

      • Kees Goossens, Om Prakash Gangwal, Jens Röover, A.P. Niranjan

      Pages 399-423

In Interconnect-centric Design for Advanced SoC and NoC, we have tried to create a comprehensive understanding about on-chip interconnect characteristics, design methodologies, layered views on different abstraction levels and finally about applying the interconnect-centric design in system-on-chip design.
Traditionally, on-chip communication design has been done using rather ad-hoc and informal approaches that fail to meet some of the challenges posed by next-generation SOC designs, such as performance and throughput, power and energy, reliability, predictability, synchronization, and management of concurrency. To address these challenges, it is critical to take a global view of the communication problem, and decompose it along lines that make it more tractable. We believe that a layered approach similar to that defined by the communication networks community should also be used for on-chip communication design.
The design issues are handled on physical and circuit layer, logic and architecture layer, and from system design methodology and tools point of view. Formal communication modeling and refinement is used to bridge the communication layers, and network-centric modeling of multiprocessor on-chip networks and socket-based design will serve the development of platforms for SoC and NoC integration. Interconnect-centric Design for Advanced SoC and NoC is concluded by two application examples: interconnect and memory organization in SoCs for advanced set-top boxes and TV, and a case study in NoC platform design for more generic applications.

• Routing
• SoC
• architecture
• communication
• integrated circuit
• layers
• modeling
• network on chip (NoC)
• simulation
• single-electron transistor
• system on chip (SoC)

From the reviews:

"…a collection of edited chapters written by various experts on NoC and on-chip communications design; the editors contributed to several of the chapters and, for the others, drew on several colleagues—including those participating in Complain, the Finnish-Swedish Excite research project. The editors have carefully chosen the topics in this volume to reflect the multiple levels and types of design knowledge required to gain an appreciation of the field… this book is quite useful for educating any SoC design team in many of the areas critical to adapting their designs to future generations of interconnect. It can also be a useful reference text for advanced undergraduate- and graduate-level courses in SoC and VLSI design. Designers and design educators should take a close look at this book."
(IEEE Design & Test of Computers Magazine)

"The book is a collection of edited chapters written by various experts on NoC and on chip communications design … . The editors have carefully chosen the topics in this volume … . Clearly, the book covers an impressive breadth of topics … . Each chapter surveys the relevant literature in its particular topic area and provides an extensive reference list … . a useful reference text for advanced undergraduate- and graduate-level courses in SoC and VLSI design. Design and design educators should take a close look at this book." (Grant Martin, IEEE Design & Test of Computers, March-April, 2005)

 

 

• Tampere University of Technology, Finland

  Jari Nurmi

• Royal Institute of Technology, Sweden

  Hannu Tenhunen, Axel Jantsch

• University of Turku, Finland

  Jouni Isoaho

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