Overview
- Covers in detail an efficient design methodology from system specifications to Silicon implementation that reduces silicon re-spin by meeting specifications first time round
- Covers in great detail all design and implementation issues associated with Delta-Sigma based Fractional-N synthesizers
- Provides an efficient modelling and simulation technique that can be applied both open loop and close loop to accurately predict the designed synthesizer performance
- The developed techniques in the book can help in designing very low noise, high speed fractional-N frequency synthesizers
Part of the book series: Analog Circuits and Signal Processing (ACSP)
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Table of contents (7 chapters)
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Front Matter
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Back Matter
Keywords
About this book
Recently, wireless LAN standards have emerged in the market. Those standards operate in various frequency ranges. To reduce component count, it is of importance to design a multi-mode frequency synthesizer that serves all wireless LAN standards including 802.11a, 802.11b and 802.11g standards. With different specifications for those standards, designing integer-based phase-locked loop frequency synthesizers can not be achieved. Fractional-N frequency synthesizers offer the solution required for a common multi-mode local oscillator. Those fractional-N synthesizers are based on delta-sigma modulators which in combination with a divider yield the fractional division required for the desired frequency of interest.
In CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications, the authors outline detailed design methodology for fast frequency hopping synthesizers for RF and wireless communications applications. Great emphasis on fractional-N delta-sigma based phase locked loops from specifications, system analysis and architecture planning to circuit design and silicon implementation.
The book describes an efficient design and characterization methodology that has been developed to study loop trade-offs in both open and close loop modelling techniques. This is based on a simulation platform that incorporates both behavioral models and measured/simulated sub-blocks of the chosen frequency synthesizer. The platform predicts accurately the phase noise, spurious and switching performance of the final design. Therefore excellent phase noise and spurious performance can be achieved while meeting all the specified requirements. The design methodology reduces the need for silicon re-spin enabling circuit designers to directly meet cost, performance and schedule milestones.
The developed knowledge and techniques have been used in the successful design and implementation of two high speed multi-modefractional-N frequency synthesizers for the IEEE 801.11a/b/g standards. Both synthesizer designs are described in details.
Authors and Affiliations
Bibliographic Information
Book Title: CMOS Single Chip Fast Frequency Hopping Synthesizers for Wireless Multi-Gigahertz Applications
Book Subtitle: Design Methodology, Analysis, and Implementation
Authors: Taoufik Bourdi, Izzet Kale
Series Title: Analog Circuits and Signal Processing
DOI: https://doi.org/10.1007/978-1-4020-5928-5
Publisher: Springer Dordrecht
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer Science+Business Media B.V. 2007
Hardcover ISBN: 978-1-4020-5927-8Published: 14 March 2007
Softcover ISBN: 978-90-481-7478-2Published: 19 November 2010
eBook ISBN: 978-1-4020-5928-5Published: 06 March 2007
Series ISSN: 1872-082X
Series E-ISSN: 2197-1854
Edition Number: 1
Number of Pages: XII, 208
Topics: Communications Engineering, Networks, Microwaves, RF and Optical Engineering, Circuits and Systems, Electronics and Microelectronics, Instrumentation