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CMOS Multichannel Single-Chip Receivers for Multi-Gigabit Optical Data Communications

  • Book
  • © 2007

Overview

Authors:
  1. Paul Muller

    1. Marvell Semiconductor, Etoy, Switzerland

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    You can also search for this author in PubMed   Google Scholar

  2. Yusuf Leblebici

    1. École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland

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    You can also search for this author in PubMed   Google Scholar

  • Focus on CMOS-based receiver design
  • Focus on short-distance communication aspects
  • Unique system-level receiver analysis and resulting top-down design methodology
  • Presentation of mathematical models for clock recovery jitter tolerance analysis

Part of the book series: Analog Circuits and Signal Processing (ACSP)

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Table of contents (8 chapters)

  1. Front Matter

    Pages i-xx
    Download chapter PDF

  2. Introduction

    • Paul Muller, Yusuf Leblebici
    Pages 1-4

  3. Integrated Photonic Systems

    • Paul Muller, Yusuf Leblebici
    Pages 5-11

  4. Basic Concepts

    • Paul Muller, Yusuf Leblebici
    Pages 13-28

  5. System-Level Specifications

    • Paul Muller, Yusuf Leblebici
    Pages 29-55

  6. Silicon Photodetectors

    • Paul Muller, Yusuf Leblebici
    Pages 57-72

  7. Transimpedance Amplifier Design

    • Paul Muller, Yusuf Leblebici
    Pages 73-93

  8. Limiting Amplifier Design

    • Paul Muller, Yusuf Leblebici
    Pages 95-126

  9. Clock and Data Recovery Circuit

    • Paul Muller, Yusuf Leblebici
    Pages 127-180

  10. Back Matter

    Pages 181-191
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Keywords

About this book

The intention of this book is to address a number of timely, performance-critical issues within the field of short-distance optical communications, from a circuit designer’s perspective. It discusses the major trade-offs the designer has to deal with in the development of monolithically integrated receivers in CMOS technologies. As such, it is based on Dr. Muller’s doctoral dissertation entitled “A Standard CMOS Multi-Channel Single-Chip Receiver for Multi-Gigabit Optical Data Communications”, subm- ted to the School of Engineering of the École Polytechnique Fédérale de Lausanne (EPFL) in May 2006. The dissertation material has been enhanced by the presentation of a number of alternative design approaches and circuit topologies, providing exhaustive coverage of the state of the art in optical sho- distance receiver circuit design. The need for a new processor input/output (I/O) interface paradigm is dictated by ongoing te- nology scaling and the advent of multi-core systems. Indeed, each new generation of microprocessors and digital signal processors provides higher computing power and data throughput, whereas the available bandwidth of the I/O interfaces is subject to much slower growth. Moving beyond - coming serial links to an optical data link paradigm for very short-distance (board-to-board and chip-- chip communications allows for considerable I/O interface bandwidth enhancement. Fully integrated silicon CMOS receivers are considered to be the technology of choice to lead this solution to economic success, because monolithic integration results in lower volume-manufacturing cost, improved yield and reduced assembly and test expenses.

Authors and Affiliations

  • Marvell Semiconductor, Etoy, Switzerland

    Paul Muller

  • École Polytechnique Fédérale de Lausanne, Lausanne, Switzerland

    Yusuf Leblebici

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