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  • Textbook
  • © 2002

The Verilog® Hardware Description Language

  • Presents the language using a tutorial approach
  • Provides numerous examples that allow the reader to learn by example
  • Includes a tutorial introduction to the language, a rigorous presentation of the language’s modeling constructs, and the more specialized topics of the language
  • Includes supplementary material: sn.pub/extras

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Table of contents (11 chapters)

  1. Front Matter

    Pages i-xxi
  2. Logic Synthesis

    Pages 35-71
  3. Behavioral Modeling

    Pages 73-107
  4. Concurrent Processes

    Pages 109-142
  5. Module Hierarchy

    Pages 143-155
  6. Logic Level Modeling

    Pages 157-193
  7. Advanced Timing

    Pages 211-238
  8. User-Defined Primitives

    Pages 239-250
  9. Switch Level Modeling

    Pages 251-282
  10. Projects

    Pages 283-292
  11. Back Matter

    Pages 293-381

About this book

XV From the Old to the New xvii Acknowledgments xx| Verilog A Tutorial Introduction Getting Started 2 A Structural Description 2 Simulating the binaryToESeg Driver 4 Creating Ports For the Module 7 Creating a Testbench For a Module 8 Behavioral Modeling of Combinational Circuits 11 Procedural Models 12 Rules for Synthesizing Combinational Circuits 13 Procedural Modeling of Clocked Sequential Circuits 14 Modeling Finite State Machines 15 Rules for Synthesizing Sequential Systems 18 Non-Blocking Assignment ("

Authors and Affiliations

  • Carnegie Mellon University, Pittsburgh, USA

    Donald Thomas

  • Sigmatix, South Hampton, USA

    Philip Moorby

Bibliographic Information

Buy it now

Buying options

eBook USD 64.99
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
Softcover Book USD 84.99
Price excludes VAT (USA)
  • Compact, lightweight edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Other ways to access