Editors:
- Focuses on the foundry-based process technology for the fabrication of 3-D ICs
- Discusses the technology platform for pre-packaging wafer level 3-D ICs
- Includes chapters contributed by various experts in the field of wafer-level 3-D ICs process technology
Part of the book series: Integrated Circuits and Systems (ICIR)
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Table of contents (15 chapters)
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Front Matter
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Back Matter
About this book
Editors and Affiliations
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School Electrical & Electronic Eng., Photonics Res. Centre, Nanyang Technological University, Singapore, Singapore
Chuan Seng Tan
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Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, U.S.A.
Ronald J. Gutmann
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Dept. Electrical Engineering, Massachusetts Institute of Technology, Cambridge, U.S.A.
L. Rafael Reif
Bibliographic Information
Book Title: Wafer Level 3-D ICs Process Technology
Editors: Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif
Series Title: Integrated Circuits and Systems
DOI: https://doi.org/10.1007/978-0-387-76534-1
Publisher: Springer New York, NY
eBook Packages: Engineering, Engineering (R0)
Copyright Information: Springer-Verlag US 2008
Hardcover ISBN: 978-0-387-76532-7Published: 19 September 2008
Softcover ISBN: 978-1-4419-4562-4Published: 08 December 2010
eBook ISBN: 978-0-387-76534-1Published: 29 June 2009
Series ISSN: 1558-9412
Series E-ISSN: 1558-9420
Edition Number: 1
Number of Pages: XII, 410
Topics: Electronics and Microelectronics, Instrumentation, Optical and Electronic Materials, Surfaces and Interfaces, Thin Films, Engineering, general