Wafer Level 3-D ICs Process Technology

1. Front Matter

   Pages 1-14

   PDF

2. Overview of Wafer-Level 3D ICs

   • Chuan Seng Tan, Ronald J. Gutmann, L. Rafael Reif

   Pages 1-11

3. Monolithic 3D Integrated Circuits

   • Christopher Petti, S. Brad Herner, Andrew Walker

   Pages 1-17

4. Stacked CMOS Technologies

   • Mansun Chan

   Pages 1-17

5. Wafer-Bonding Technologies and Strategies for 3D ICs

   • Shari Farrens

   Pages 1-35

6. Through-Silicon Via Fabrication, Backgrind, and Handle Wafer Technologies

   • Sharath Hosali, Greg Smith, Larry Smith, Susan Vitkavage, Sitaram Arkalgud

   Pages 1-32

7. Cu Wafer Bonding for 3D IC Applications

   • Kuan-Neng Chen, Chuan Seng Tan, Andy Fan, L. Rafael Reif

   Pages 1-14

8. Cu/Sn Solid–Liquid Interdiffusion Bonding

   • A. Munding, H. Hübner, A. Kaiser, S. Penka, P. Benkart, E. Kohn

   Pages 1-39

9. An SOI-Based 3D Circuit Integration Technology

   • James Burns, Brian Aull, Robert Berger, Nisha Checka, Chang-Lee Chen, Chenson Chen et al.

   Pages 1-26

10. 3D Fabrication Options for High-Performance CMOS Technology

    • Anna W. Topol, Steven J. Koester, Douglas C. La Tulipe, Albert M. Young

    Pages 1-21

11. 3D Integration Based upon Dielectric Adhesive Bonding

    • Jian-Qiang Lu, Timothy S. Cale, Ronald J. Gutmann

    Pages 1-38

12. Direct Hybrid Bonding

    • Bart Swinnen, Anne Jourdain, Piet De Moor, Eric Beyne

    Pages 1-11

13. 3D Memory

    • Robert S. Patti

    Pages 1-23

14. Circuit Architectures for 3D Integration

    • Nisha Checka

    Pages 1-13

15. Thermal Challenges of 3D ICs

    • Sheng-Chih Lin, Kaustav Banerjee

    Pages 1-26

16. Status and Outlook

    • Scott K. Pozder, Robert E. Jones

    Pages 1-20

17. Back Matter

    Pages 1-7

    PDF

Three-dimensional (3D) integration is clearly the simplest answer to most of the semiconductor industry’s vexing problems: heterogeneous integration and red- tions of power, form factor, delay, and even cost. Conceptually the power, latency, and form factor of a system with a ?xed number of transistors all scale roughly linearly with the diameter of the smallest sphere enclosing frequently interacting devices. This clearly provides the fundamental motivation behind 3D technologies which vertically stack several strata of device and interconnect layers with high vertical interconnectivity. In addition, the ability to vertically stack strata with - vergent and even incompatible process ?ows provides for low cost and low parasitic integration of diverse technologies such as sensors, energy scavengers, nonvolatile memory, dense memory, fast memory, processors, and RF layers. These capabilities coupled with today’s trends of increasing levels of integrated functionality, lower power, smaller form factor, increasingly divergent process ?ows, and functional diversi?cation would seem to make 3D technologies a natural choice for most of the semiconductor industry. Since the concept of vertical integration of different strata has been around for over 20 years, why aren’t vertically stacked strata endemic to the semiconductor industry? The simple answer to this question is that in the past, the 3D advantages while interesting were not necessary due to the tremendous opportunities offered by geometric scaling. In addition, even when the global interconnect problem of high-performance single-core processors seemed insurmountable without inno- tions such as 3D, alternative architectural solutions such as multicores could eff- tivelydelaybutnoteliminatetheneedfor3D.

• Applications enabled by 3-D integration
• CMOS
• Diffusion
• Technologie
• Three-dimensional (3-D) integration
• Through Silicon vias (TSVs)
• Wafer
• Wafer bonding
• Wafer-Level 3-D Technology Platforms
• circuit
• design
• integrated circuit
• silicon
• technology
• three dimensional integrated circuit

• School Electrical & Electronic Eng., Photonics Res. Centre, Nanyang Technological University, Singapore, Singapore

  Chuan Seng Tan

• Center for Integrated Electronics, Rensselaer Polytechnic Institute, Troy, U.S.A.

  Ronald J. Gutmann

• Dept. Electrical Engineering, Massachusetts Institute of Technology, Cambridge, U.S.A.

  L. Rafael Reif

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